Low noise, high bias voltage on picoAmp TIA's input, howto?
May 21, 2021 Last reply: 2 years ago 62 Replies
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Joe Gwinn
Got it. Thanks.
I have already read a library copy, but wanted a copy for reference.
The key idea that is useful outside of metrology is using toroid cores around the coaxial cables to force center and shield currents to be exactly equal but opposite, like a transmission-line balun.
Joe Gwinn
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Bill Sloman
On Friday, May 28, 2021 at 11:26:41 PM UTC+10, Bill Sloman wrote:
Here's a more conventional LT Spice model of a MOSFet driven inverter.
Seems to work. Startup is messy. The MOSFet was picked from what LT Spice offered - it isn't all that cheap. The transformer is what Timo seems to have used, but I haven't worked out wire sizes and layering. The single turn winding - L5 - would presumably be at the bottom pf the stack, tucked in a corner under the centre-tapped primary, which I'd probably wind as as 15 turns of twisted pair. The secondaries are 80 turns each, which might be one layer each of 0.1mm wire - maybe 0.6mm with there layers of 0.06mm tape - but you still have 1.6 mm of height for the primaries, which should be plenty. Two layer secondaries might work too.
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timo.k...
Bill Sloman
28.05.2021, 15:26:41 (vor 4 Tagen)
Hi Bill,
Excuse for the delay, please!
The simulation run always better without ferrites at the end, the inductance produced ringing.
Yes, it should! Because the load changes at this time.
I fiddled around with some vriations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits. The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents.
Wer are "lucky" to have the "time" problem only. I am the only one working on the analog part of this (and a few other) projects. Mostly we have to deliver only a few modules/systems to our scientific customers. So the part costs are not the main issue in most cases.
Hmm, for sure? I don't know exactly. See
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Abb. 7.25: The oscillator was not optimised for no-load conditions, see Ic(Q1/2) spikes and it’s negative part. Raising the value of R11 compensates it. Even the choke current goes partly negative. Raising the choke’s value lowers amplitude of the current and prevents it from going negative. Abb. 7.26: Effects of raising the values of R11 and the choke.
In my opinion the BJT based variant seems to be more robust, more simple and has a smoother startup. The latest simulations showed >80% overall efficiency at 250kHz except core losses, which haven't been simulated. The no load power consumption is safely below 500mW (partly below 250mW). After all I trust the simulation in principle (because the circuit behaved very similar on the bench) and will build up (wind the transformer) the latest version for tests.
Your last circuit runs the simulation promptly but does not start nor oscillate normally. One cycle in 2ms. At least on my PC (LTSpice17). Maybe, the LTSpice versions behave different?
Thank you! Cheers, Timo
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Bill Sloman
Real circuits use ferrite beads to contain ringing.
That doesn't tie up with what was going on.
If you use a large inductor (as you did) start up does involve the centre-tap voltage going well above what you see when the circuit has settled down, and the inductor pulling the centre-tap below ground during start-up. With bipolar transistors this gets you into squegging, which persists. If you put a high voltage zener between the centre-tap and ground - something like 40V - it will cap the centre tap-voltage, when it goes over 38V, and divert the negative current to ground, and the start-up would be briefer and cleaner.
The messy start-up isn't a consequence of the FET drive.
Simulations aren't real life.
You may need to revise that opinion. The start-up isn't a problem with actual circuits I've worked with, unless it persists - when it is called squegging.
Baxandall's paper only refers to it in a footnote on page 752. I've run into it in real life, and the late Tony Williams had seen more of it than he liked. It's not problem that persists with MOSFet drive.
Starting oscillators in LTSpice is pest. Real circuits have enough asymmetry so they start up fast. Simulated circuits are much more symmetrical.
My circuit did take a few msec start, which is why I let the simulation run for 10msec to let it settle down. You can fiddle the initial conditions to get them to start faster, but that takes work and it's rarely worth the effort.
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Bill Sloman
In fact what was going on was that the current though feed inductor L6 - went up to 12.6A before the oscillator started oscillating at all, and it started off at 7kHz, moving up to 100kHz with about a millisecond.
You power supply isn't going to deliver 12A and real components are different enough that the oscillation would have got going earlier.
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Dmitriy Pshonkin
You can eliminate interference in active ways:
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JM
Note that the IET published a book co-authored by Kibble called "Coaxial Electrical Circuits for Interference-free Measurements" which is still in print. It covers the information in Kibble's earlier book.
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Bill Sloman
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I've tweaked my simulation by adding 22R to the 24V source, which pulls the initial peak current through L6 down to less than an amp. I threw in a zener to limit the peak centre tap voltage, but added a ferrite bead to kill some very high frequency ringing which showed up on the capacitative current through the zener in regular operatoin.
A Resonant DC-DC transformer with Zero Current Ripple
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Bill Sloman
It costs money to see it. The Cuk converter from 1983
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offered ripple-free output (if I remember rightly - and I had to dig a bit to come up with the name). I looked at it at the time, and it looked a bit expensive for what it offered.
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Gerhard Hoffmann
Am 12.06.21 um 11:19 schrieb Dmitriy Pshonkin:
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Bill Sloman
It looks cute. I particularly like the idea of winding the input inductor and the output filter inductance on the same core - they are coping with the same series of half-sine wave voltages, after all. To paraphrase Thomas Huxley on Darwin's Theory of evolution, I do feel a bit stupid for not thinking of it for myself.
Here's a version of Timo's +/-200V inverter that incorporates the idea. It's not in the least ripple free - there's about 80mA of ripple on the roughly 12mA DC current through the inductor L6, but there's very little voltage ripple on the 200V output - some 200mV. The turns ratio had to be pushed up appreciably to get 200V DC out - the circuit isn't peak-clipping any more.
There is a significant 1.8MHz component in the ripple current - it should be possible to work out where this coming from and damp it down, but it's not worth the trouble on a Spice simulation, though it would be worth doing if it showed up on a real circuit.
Thank you guys, fro all your valaubel hints! I do not have enough time to answer something useful in the moment. Nevertheless I try to understand and "replay" all the ideas, especially the coupled inductors one, which looks very interesting. Unfortunately I am very bad in math, so I have to "guess" the right Lin/Lf values out of the paper. My version of the HV linear regulator for Bias seems to be okay, an AC simulation shows up to 100dB ripple rejection, I didn't measure it on the bench until now. It does not need to have high upper frequency corner. The amplitude response of 1Hz max. is enough for this application. See 20210531_FAMEIO_SuperSIMS-MV40-Ersatz_S44.pdf in the actualised link
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your last *.asc does not oscillate in my environment, maybe, I did something wrong. Thanks! Cheers, Timo
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Bill Sloman
Works fine for me. I updated LT Spice 17 a couple weeks ago. If you've done it more recently it may not be quite the same environment.
My start-up is still pretty horrible - Vtank peaks at 128V at about 12 usec, and I(6) at 1.34A at about 7.5usec. Regular oscillation sets in at about 56usec and it has more or less settled down by 500usec.
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Bill Sloman
Oops. Not such a good job after all. I should have flipped L8 though 180 degrees when I originally cut and pasted it from L7.
Woke up in the middle of the night wondering whether I'd bother to do it. and when I checked. I hadn't.
I've done it here. Doesn't seem to have made much difference to the waveforms that I'd bothered to look at, which doesn't say anything good about my attention to detail
Even more oops. The extra windings were in the wrong place, and when I put them where I think they ought to go the circuit behaves in a way that it shouldn't.
I found a couple more bugs when I started looking harder, and I don't think I've got rid of all of them yet. Depressing, but design is like that, until you get it right, if you can.
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tiki
Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:
Hello,
same to me. Didn't get it working in a meaninful manner. ;) Neither did my attempt work as shown in the paper. So I strip it down to the bones now, but still...
On the other hand does the heavily loaded BJT based version for all the lower voltages (without the second L in the output) produce somewhat irregular waveforms, getting closer to rectangle shape but still much less harmonics than a hard switching version. It seems to be clear due to the energy, which the load draws out of the output, so the rectifiers must cut the tops of sine. Something like an in-between of Baxandall and hard-switched Push pull, but still resonating. And load helps to prevent "squegging" - safely in my tries. Thank you for your effort! It's still very interesting! :)
Cheers, Timo
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Bill Sloman
The oops wasn't as bad as I first thought. This is the current version, which isn't all that different from the last one. It seems to work for me, despite a slightly more realistic value (10pF rather than 1pF) for the parallel capacitances of the overwindings (l7 and L8) on the feed-inductor - L6. The overwindings just cancel out the half-sine component of the voltages applied to L11 and L12 leaving something closer to a constant voltage. It still strikes me as a neat idea.
I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them.
This is about as simple as the circuit can get. The MOSFets are driven by a centre-tapped 6-turn winding (L5 and L6) and the EFD55-8 former has only got eight pins, which means that on a real circuit you'd have to improvise a bit.
For the circuit to start the bias voltage on the centre tap has to be just high enough for both MOSFets to be turned on, which is a bit too high to let the circuit work properly once it running as intended. The network around D6, D7 and D8 lets bias voltage get pulled down to the point where the circuit will work correctly, once it is operating as intended.
With values chosen, each of D7 and D8 is pulling current out of the bias node for about a quartrer the time, and I imagine that that will probably work over the tolerance range for the MOSFets M1 and M2 - Siliconix Si3.440DV parts which happened to be in the LT Spice component range.
R8 damps the 2.5MHz parastic oscillation driven by the switching transients. A more complex design could have smaller switching transients, but it wouldn't be worth posting here.
L14 is a totally dummy part - it exists to create the waveform V(cancelingV) which is there to make it easier to explain what L8 an L9 were put in to do. If you plot V(n009) + V(cancellingv) or V(n018) - V(cancellingv) you get pretty close to flat +200V and -200V traces, which are a lot easier to filter than the voltage coming out of the rectifiers.
The circuit seems to deliver 4mA at +200V and -200V - 1.6 Watt - and draw 81mA at 24V - 1.95 Watt, which 82% efficiency. Two mA of the current drawn is setting up bias voltages. The inductor resistances aren't properly worked out, so this isn't all that reliable.
I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across.