linear ramp

In fixed-spaced font:

Jon

If extreme ramp linearity is needed, say at the 12-bit level, it gets more interesting. One thing to do is make the current change as a function of ramp level. Given a current source, to bow the curve down is easy: add a resistor to ground across the ramp cap. To bow it upward, arrange for the current to increase during the ramp. If the current source is a PNP, a resistor from the opamp output to the emitter does that. Or if you add an opamp follower in the bootstrap loop, just give it a little gain.

Or do both upward and downward curves and tweak them against one another for best linearity. That allows tweaking out miscellaneous nonlinear junction capacitances, too.

Of course, at 12 bit linearity, the schottky diode forward drop vs temperature, and its leakage, become problems, so it has to go.

John

I'm sure it's possible to make that go away with a bandaid, but it'd probably be simpler to use an R-S flipflop, a current-steering diff pair, and a comparator that resets the flipflop at the end of the ramp. Since you have a long time for reset, that could be done with two resistors with a bootstrap cap to the output--since there's zero volts across the resistor in the quiescent state, there'd be almost zero throughout the ramp, and the resistor could be large anyway. (The two effects together would make the error quadratic in the duty cycle, I think, so it the DC wouldn't have to be 10**-4.) If you used a little bit of noniverting gain, you could tweak out the Early effect in the transistor with a bit of positive feedback.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

On a sunny day (Fri, 08 Apr 2011 01:53:26 -0700) it happened Jon Kirwan wrote in :

Hey, cool, thank you. What is the advantage of this over say this?

+15 | R | | < +5-----| PNP |\ |---- | |__| --- --| |---- --- |--| | | /// ///

No Early effect, and no V_BE drift.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

Here's one I did, a long time ago, with current steering...

ftp://jjlarkin.lmi.net/22S880A.pdf

and you're right, you get a very precise reset voltage if you turn the current source off when you don't need it.

This one was over-designed out of too much caution; it would be a lot simpler today. The comparator was the ill-fated MAX9690, which had to be replaced with a kluge:

ftp://jjlarkin.lmi.net/OnBoard.jpg

The product itself worked out pretty well.

John

Does the P400 have that circuit in it?

What's R276 for?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

And no transistor oscillation, or ramp curvature from C-B and D-S capacitance modulation. And no need for super-regulated power rails.

Actually, I originally drew up something like that, with precision rails that included Vbe temperature compensation, and a couple more parts to avoid the other side effects, and an open-drain TinyLogic buffer for discharge. It wasn't bad, but I like the bootstrap thing better. I only need three ramp circuits per board in this application, so it's about a wash on parts count.

Just thought talking about actual electronics would be a change from rusty barbeques and redneck political rants.

John

hairy,

No, that was for the NIF timing system.

There was a little ringing at the start of the ramp, probably a PC layout artifact, and that killed it. One lesson: always work against ground.

John

Ah, okay. IIRC it was a low noise reference, so maybe it added 10-12nV RMS noise at the instrument input, which is pretty much down in the grass.

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We set up a similar ramp for the electron beam tester back in 1990, and solved the schottky diode forward drop problem by letting the system recalibrate itself every few minutes - we were using one ramp to digitise the delay from an unsynchronised trigger and the next but one 800MHz system clock edge, and a second ramp to generate a delay from a specific clock edge to well-controlled sampling pulse, and by cross-linking these two gadegets we could recalibrate both of them automatically, on the fly.

But we were only going for 8-bit resolution - 5psec in 1.25nsec - and the jitter on the 800MHz clock was appreciably more than 5psec.

-- Bill Sloman, Nijmegen (but at a new address)

Looks good to me, excepting the probable startup glitch, and the startup level may be temperature dependent. Getting sufficient linearity was always the easy part with 'scope timebases - it was the startup that was the key to success. Having this be a fixed rate ramp should make this much easier. Are you concerned about recovery time?

I can ignore the first volt of the ramp anyhow! I just need a couple of volts of precise sweep region.

Not much. I need to make a 20 ns ramp every 10 us, roughly.

One interesting note: the forward drop TC of a small schottky diode increases as current goes up, hitting zero at some practical current. This particular diode will be around 0.7 mv/K at 5 mA or so, substantially better than the 2.5 mv/K one usually expects from a diode. At the system level, we can tolerate that. Besides, this will be in a clean room whose temperature pretty much never changes.

John

I'm timing things to 8 bits resolution here, 62 ps LSB, but could tolerate 1% ramp error. Overkill to keep the customer happy.

As noted, the schottky drop TC will be well under 1 mv/K at my operating current. As current goes up, the ohmic drop, which has a positive TC, cancels the junction's negative TC. There are schottkies with zero forward TC at currents like 5 or 10 mA.

John

On a sunny day (Fri, 08 Apr 2011 10:26:50 -0400) it happened Phil Hobbs wrote in :

What exactly do you mean by 'early effect'?

Vbe drift can be compensated for by adding a diode, but it still needs stable supplies.

It'd be interesting to look at the curvature of the combined V_F vs T plot.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

That's pretty quiet for a reference, even in a 1-hertz bandwidth. Most of them stink on ice.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

Early effect is the variation of collector current with V_CE at fixed V_BE, caused by modulation of the effective base width by the change of the C-B depletion zone width. To leading order it looks like a conductance from collector to emitter, but in real devices there's a lot of curvature. It spoils a lot of conceptually nice BJT circuits, almost as many as Miller capacitance.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

On a sunny day (Fri, 08 Apr 2011 15:00:20 -0400) it happened Phil Hobbs wrote in :

OK, I know about Miller, I was thinking in this circuit Vbe is not exactly fixed, but it is more that Ic and Ie are related, in the sense that for a high enough beta IC is almost Ib. (less than 1% error for a beta > 100). Is this not true for this case with the capacitor voltage at zero, all the way up to a few volt (but still way below saturation)?