Incandescent lamp inrush current vs. regulated power supplies

As long as it does not shut itself down, would work.

Greg

Do you need DC ?

Greg

But foldback will further reduce output voltage (not current) putting you right in that box.

In some situations, that may be true. In others, untrue. For the OP's load with negative resistance, foldback is a bad idea.

For the general case, it may be possible to design the load to draw low current at low voltage, e.g. by means of a UVLO. In that case foldback current limiting doesn't cause system problems at all if the UVLO threshold is higher than the voltage at which the foldback current limit kicks in.

Regards, Allan

I don't see a case where it's wanted (for a switcher).

The above doesn't make any sense to me. If the load/PS are designed for, say, 10V, how is the voltage going to decrease *and* the current decrease?

is

should

Not sure where you first saw this thread but OP in sed has a lamp load.

?-)

As follows:

I knew it was an incandescent lamp. I understand the static and dynamic VI characteristics of such a load, and their implications for driver design.

My negative resistance comment was the result a brain fart - I was thinking about a completely different system with a DC/DC converter as a load and somehow got that mixed up in my post.

Allan

As I said earlier, it can save money in certain designs.

It would only be useful under the following conditions:

- the usual duty cycle of the DC/DC converter is quite high (i.e. Vout/ Vin is close to 1). This in turn means that the bottom FET can be quite small compared to the top FET.

- The load doesn't need a lot of current at low voltages.

- The design must tolerate short circuits on the output.

- There is no hiccup or other mechanism to protect the bottom FET during a short.

During a short on the output, the duty cycle will drop to close 0. The bottom FET will be on most of the time, conducting the full output current. This is the worst case for the bottom FET. Its power dissipation may be several times what it is for normal full load.

The top FET, OTOH, has a fairly easy time during an output short.

The designer has a choice: size the bottom FET (and its heatsinking) for this worst case, or reduce the average current somehow. Often the average current is reduced with a hiccup (periodic shutdown and restart) but it is also possible to use foldback current limiting.

For the small DC/DC converters I usually design, the FETs are cheap and there is no heatsinking, and I have never used foldback current limiting.

I have seen it done on larger designs (by other people) though.

UVLO stands for Under Voltage Lock Out. The load turns itself off if the voltage is less than a certain amount. BTW, this doesn't help the OP's problem with incandescent lamps, but it can be quite useful if the load is something like a buck converter. For your 10V example, the buck converter input current will increase as the input voltage decreases. When it gets below the UVLO threshold (say at

7V) the current drops to zero.

I seem to work with a lot of systems that have intermedate bus voltages that come from a DC/DC converter with loads are also DC/DC converters. Managing the inrush so everything comes up cleanly without hiccups requires some attention to detail, but isn't too hard to get right.

Regards, Allan

Topology? The rest of this makes no sense without knowing the topology.

This doesn't make sense. At low voltage it *is* taking a lot of current. That's how we got here.

Constant current takes care of this.

You snipped some text containing the word "buck". It's a buck converter.

Alone, yes, a constant current limit will protect the bottom FET. But with the other conditions that you snipped (so as to misrepresent my argument) a constant current limit may result in the bottom FET dissipating many times its normal power when the output is shorted to ground.

I'm fairly sure you understand the concept.

Allan

People get pissed if one doesn't snip and they get pissed if you do. Ah, well...

OK, but this makes even less sense.

I wasn't intentionally misrepresenting your argument. I'm trying to snip out the irrelevant issues. You type a lot. ;-)

What other conditions. I'm still not seeing it.

I think I do but I don't see your point.

putting

low

foldback

limit

load.

Hadn't met you before, didn't know you are a full member of the club.

?-)

The other conditions that you ask about were ones you described as irrelevant and snipped.

Would a contrived example help?

Buck DC/DC converter.

10V input. 8V ouput. 10A current limit. 10mohm FETs Ignore switching losses. Assume the inductance ie large and delta-I is small.

Under normal conditions, the duty cycle will be approx. 80%. The top FET is on 80% of the time and the bottom FET is on 20% of the time.

At full load (10A output current), the top FET dissipates 0.8W and the bottom FET dissipates 0.2W.

(Now we design the heatsinking to handle 0.8W for the top FET and 0.2W for the bottom FET.)

Now short the output to ground. The output current is still 10A, but now the duty cycle is close to 0%, i.e. the top FET is almost never on, and the bottom FET is on almost all the time. The top FET disspates very little power, and the bottom FET now dissipates 1.0W.

So, with no change in output current, the power dissipated by the bottom FET increased by a factor of 5 when the output was shorted.

You could waste money by putting in a bigger heatsink to handle this case, or you could do something smart like make the controller hiccup or you could add foldback current limit.

I don't advocate the use of foldback current limit for most DC/DC converters, but you can see that in special cases like this one (with a high Vout/Vin ratio) that it can potentially make the design cheaper.

Regards, Allan