I'm popping MOSFETS....linear derating factor involved?

I read a paper a while back on this phenomenon applied to TO-247. IEEE trans. power electronics IIRC.

its a huge issue with DCB IGBT modules, and one of the reasons big thyristors are all press-pack.

the junction always heats up faster than the case, thats what causes the problem.

lets look at the model for the infineon SPP04N60C3.

Rth Cth Tau

0.039 0.00007347 2.86us this is the junction 0.074 0.0002831 21us 0.132 0.0004062 54us 0.555 0.001215 674us 0.529 0.00276 1.46ms 0.169 0.029 4.9ms

so the junction thermal time constant is an order of magnitude smaller than the next quickest one, and > 1000x slower than the tab....

one of the fun things you can do with repetitive overloads is ratchet Tj up while the tab stays fairly cool.

I dont know how applicable those curves are to TO-220/TO-247, but the general argument is a mechanical one, so the trend will be similar.

I stick to a few simple rules, and have very little trouble (and I've built some BIG smps)

- solid 0V plane, no slots

- nice low impedances everywhere

- lots of UVLO-type circuitry, to ensure power-up and power-down is fully controlled (lots of nasties happen with wobbly supplies)

- keep my H fields contained (eg magnetics)

- try to avoid huge E-field radiators

no worries mate :)

LTSPICE, from linear technology. free, powerful, and a plethora of skilled users haunt SED. draw your RC circuit, set up the pulse characteristics of your current source and off you go.

I've done quite a few electro-thermal simulations. Infineon (IIRC) have FET models with a Tj input (Rdson varies with Tj) so your spice circuit model can measure Pfet, run it throu the actual thermal model to calculate Tj, and feed that back into the FET model.... great stuff.

Cheers Terry

Just installed it, thanks! Funny thing is that I've heard about SwitcherCAD but never knew that it was based on SPICE.

John

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We've been shipping NMR gradient drivers for over 10 years. Various units have from two TO-220s (3 amp versions) up to 32 TO-247s (100 amp, 17 KW peak out.) All run pulsed at 5-10% duty cycle and all push the junction temps 50-80C per pulse, roughly one pulse per second. They run a lot, since the machines are busy and expensive.

So far, we're not seeing any evidence of a fet wearout mechanism.

John

Hi John,

any particular brand of FET? what sort of duty do the amps actually see? thats a whole lot of cycles.

the problem will be related to the die area, as its tempco mismatch causing the strain. many smaller die = the way to go.

I'll have a hunt for that paper....

Cheers Terry

I believe I've found a cause for at least one of my FET-popping incidents. When the circuit is powered up and the battery to be drained is not connected to the LOAD+ and LOAD- terminals, the op-amp is driving the FET gates hard. If I now connect the battery, one heck of a current spike flows thru the FET for a short time until the servo loop can bring the current back down. This can't be good for the FET and probably popped at least one of them due to movement (intermittent contact) of the battery connections in my earlier prototype when I was hooking up the scope (or whatever).

I've been playing with the circuit in LTSpice (thanks again Terry!) and have not been able to find a way to slow down the circuit enough to prevent this spike. I've tried caps on the inv. and noninv. inputs of the op-amp, increasing the size of the gate cap and res. and placing a cap at the LOAD+ pin....no luck. Is it possible to prevent this spike?

John

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One thing i can tell you for sure, running your devices even near power dissipation limits severely degrade lifetime. Part of the issue is that the junction to case thermal path degrades under those conditions.

--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller

Would things work for you with 3 transistors in "parallel"? The thermal advantage is significant.

--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller

I agree, I'm REALLY pushing it. I'm doing these abusive tests to get an idea of what the limits really are and I'm slowly realizing that I will have to lower the junction temps to get a decent lifetime for these FETs.

One test I have running now is the thermal cycling. I'm at about 1500 cycles into the test without problems (125W each FET, 2 minutes on, 2 minutes off, running the fet junction from about 30C to 150C). But, I fully expect them to pop any second. :-)

John

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I originally had 4 FETs to help lower the total thermal resistance and junction temperature (going to 4 FETs lowers Tj about 40C...that's a LOT) but the PCB layout almost impossible. No room, too many compromises.

Since going to 2 FETs let me drop one of the LT1013's and its resistors/caps, I've been trying to see how far I can push just 2 FETs. That would give me enough room to lay out the PCB the way I want to and save some $$ too. Those FETs are expensive. Not as expensive as replacing blown FETs, I guess.

I think you're idea is a good one.... As a "compromise" I could go to 3 FETs but would need to add a second LT1013 and its resistors/caps. But, I'm thinking more and more that I might have to do this and will probably play with the PCB layout later this week. Adding a third FET would probably drop the junction temperature 20C and that would help a lot to increase their lifetime.

John

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If 4 won't work because of layout space and 2 won't work because of over dissipation try 3.

--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller

Wait a sec.... My problem might be that the circuit already is "too slow"! The high-am-p pule thru the FETs when I hook up the battery needs a really fast circuit to be able to sense the voltage across the source resistor (current sense resistor) and immediately adjust the gate voltage to stop the current flow.

I don't want to speed up the servo loop because a nice slow loop is good for ignoring anything that might come along during operation but I still need some way to stop that huge current pulse if the battery connection is intermnittent or the battery is connected after the circuit is powered up.

John

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thats a very real possibility :)

what you need to do is toss in something to detect a no battery condition, and clamp your setpoint to zero. When a load comes along (easy to tell as its a battery) you can then let go of the reference pin, and away it goes.

Something a control guru pointed out to me years ago was that *NO* controller can follow a step, ever. One important part of building a real-world controller is some form of ramp limiting on the reference, so you never ask for the impossible. In your case, an LM339 and a cap would do the trick.

Cheers Terry

Perhaps the mod below.

| _____________ SPCO o | |-------LOAD+ Switch /------------|Voltage sense| o/ o |_____________|-------LOAD- | | Vref--+ +--LOW-LVL GND

If the voltage across LOAD+/- is below a certain level then the bottom ends of the R3's are switched to Vref. Could be a relay, or solid state.

--
Tony Williams.

On Wed, 22 Mar 2006 19:28:29 +1200, Terry Given Gave us:

Have any of you guys ever heard of a "transzorb"?

One can also place a small ferrite bead directly on the lead of the FET to assist.

how is a transorb or a ferrite bead going to alter the fact that, sans battery, the opamp saturates?

Cheers Terry

So I would use the open-collector output of the LM339 (configured as a basic comparator, probably with hysteresis) to pull the pin ref. voltage to the servo loops down to ground (almost) when the battery was removed.....cool. :-)

Vref of the LM339 would go to some low voltage (below 0.5V, the lowest I'd ever take a battery), perhaps the servo loop Vref which is always less than 0.2V. And Vin of the LM339 would go to the positive LOAD terminal to detect the battery voltage.

Not sure where the cap you mentioned would go though. On the output of the LM339 to slow the rise of the reference voltage when the battery was attached?

John

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I like it...thanks Tony! I never cease to be amazed at how logical and simple (and often very obvious, in hindsight) a solution can be when someone else points it out. Racked my brains on this one. :-)

John

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Whoops, maybe not?

The low-level output voltage of the comparators I've been taking a peek at is 400mV to 750mV. Since my servo loop reference voltage ranges from GND to 125mV, I think I'm in trouble. I won't be able to pull the reference voltage down at all.

I guess I need an open-collector or open-drain output that can go down to almost GND, within a couple of millivolts, with a load of 1mA max. (typically 0.5mA or less).

Or have the comparator drive a FET? An IRFL014 would only have a Vds of 0.2mV at 1mA. I would drive it with an inverting comparator.

Hmm....not sure if the low-level output voltage of the comparator would be low enough to not bias the FET gate enough for that 0.5mA to

1mA of Vref current to pass through.

I could go to a reed relay instead of a FET but that would require debouncing the output with a cap? I don't want Vref for the servo loops bouncing all over the place.

John

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Shift what the comparator does.

The maximum demand voltage to all +ve inputs is 208mV. So leave Vref alone and use the comparator to bias all opamp -ve inputs to greater than 208mV instead. This fakes an apparent full-scale feedback voltage from the current shunt, and all opamps go to zero voltage output onto the FET gates.

--+--5v | _ [10k?] --|- \\ | |Comp---+-------[560k]--> Junction R3,R5. --|+_/ | | +-------[560k]--> Junction R3,R5. LOW-LVL GND | +-------[560k]--> Junction R3,R5.

Arrange the Comparator output polarity to be Low for normal operation and High when there is no voltage between LOAD+ and LOAD-.

In normal operation a 560k in parallel with R3 will change the pot scaling slightly, but not important.

--
Tony Williams.