Hi John - looking at the simulation of your circuit, I am not sure if your circuit is fast enough. If you look at the power dissipated by the FET ((V(n004)-V(n007))*I(R4)), it peaks at about 420W when switching. Wouldn't that kill the poor bastard? Additionally, I think it'd be even worse in my application, as the switched load is very inductive (about 80% of the load is motors). It looks like it takes about half a microsecond, so perhaps is that short enough that the FET would survive? How can one decide if this is safe or not? Is there a rule of thumb that I don't know?
The 55V source is a 12 cell lithium polymer battery pack. Thus 55V is a bit high, but I like to be careful.
I have a memory of looking at that Infineon part and Digi-Key telling me that it is no longer being made. But I could be remembering a different Infineon part, I'm not entirely sure. That conversation was at least a month ago.
Anyways, I would ideally like a less integrated solution, not because of cost, but because I like to turn every design into a learning opportunity, as I still have a lot of learning to do! Connecting black boxes is too easy.
By the way Winfield - are you still in Cambridge? Your e-mail address looks to be at the Rowland Institute. I run by there approximately every other morning (at around 5AM... probably before you make it in!).
I sometimes leave for work before the rush hour, and get in between 6:20 and 7:30. The problem with this is that I don't generally leave for home until 6:30 or 7pm, even if I got in early, and so getting in at 6 to 7 makes a 12-hour day, longer than I really should work at one stretch on a frequent basis. So leaving after the rush hour is my preferred approach.
You can use it in the future. :-) I also recommend ' and , -- where appropriate, instead of + everywhere, to close boxes, etc.
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well, I've been assuming some kind of quasi-close relationship between GND and RTN, but the reason for explicitly showing them separated is to avoid any logic-level and logic-threshold problems with ground drops, ground bounce, etc., with 30A loads.
Well, the scene is not as bad as you might think. In order to get low Rds(on) in the MOSFET, it's necessary to make a very large-die part. This means that it has considerable thermal mass to absorb heating during slow switching, and also that it has a large die-attachment area, which rapidly drains away heat into the package frame, and the heatsink. To understand and analyze this scene, we rely on transient thermal curves in the MOSFET's datasheet.
The Infineon switches, and parts of this class made by other manufacturers, have rather slow switching speeds -- but they are designed to handle the power dissipation resulting from the maximum rated current while switching.
Are you saying you'd like to see a full discrete-switching design, all spelled out? Ahem!
May I ask, what are the maximum ON and OFF time durations?
There are many cheap, ready-made integrated solutions to exactly this problem. It gets a bit more complicated if the high-side switch is "on" for extended periods of time, but if it reliably goes "off" every now and then there's no problem.
Since you're worried about the FET overheating I guess you have frequent switching in mind.
Nope, not frequent switching! The application is that there are a couple power sources, and each power source will be switched with a FET. A logic circuit chooses which power source to use and turns on that FET. The circuit will use that FET for probably 10-30 minutes and then once it is drained it'll switch to a difference source. That was one of the main issues I ran into when initially looking for a driver for the FET. Now I'm alot more interested in seeing if it's possible to roll my own driver.
A 160% CTR optoisolator like Fairchild's FOD617D can provide 7.5mA (min) to charge or discharge a MOSFET's gate, if the opto-s LEDs are driven by 5mA. A large- die MOSFET like an IRF1407, rated at 75V and 92A,
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with Rds(on) = 0.0078 ohms (min), has Ciss = 5600pF of gate capacitance. In particular, it takes Qgd = 54nC of charge to move the gate through the "Miller" region. That's the potentially-dangerous period during which the MOSFET is neither fully ON nor OFF, as it swings the drain voltage from one extreme to the other. The Miller capacitance is Crss = 190pF at 25V, which has to be charged by our 7.5mA of gate current.
Using t = Q/i we get 54nC/7.5mA = 7.2us. During this time the MOSFET can be dissipating what, Michael, up to 30A * 55V = 1650 watts? Not to worry, this is a big MOSFET, and it can handle massive heat for a short time by absorbing it in its thermal mass. Looking at fig 11, Effective Transient Thermal Impedance plots, we read ZthJC = 0.008 C/W for 10us. This means that we'll see only 1650 watts * 0.008 = 13C of junction- temperature rise during this "dangerous" transition.
So that issue, which you were worrying about, is fine.
Clearly one painful little problem in John's design is the dc-dc converter. But, since you're only turning the MOSFET on once every now and then, if we change the standby pulldown resistor Rs to 10M, it's clear that only a modest amount of power is required to turn on the MOSFET, enough to charge the gate capacitance, and run the 10M resistor thereafter. Well, capacitor C can be a 0.1uF, etc., and provide that gate charge, if we can find a way to charge C. My suggestion is to use another kind of opto-isolator, an extra-ordinary type, made by IR. John suggested a 9-volt battery, which isn't a bad idea, although a bit brute-force. Also, that's not a semiconductor, and is frowned upon.
Basically IR's cool part is an opto-battery, a series stack of photodiodes, powered by an LED. The PVI1050
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gives us 5uA into 10 volts (if we power it with 10mA), which we can use to charge capacitor C. Rs takes 1uA. We calculate t = CV/i = 0.1 * 10/4 = 0.25s to charge our 100nF cap. Very nice, that issue is fine too.
So, here's our new circuit.
floating MOSFET driver, JL, WH Dec07
,-----+----------, _____|_ | | in, 75V max +5 | + | | A |/ (o) ---| | | -> | | | PVI | _|_ |\\v |--' ,--| 1050 | --- C | | \\_/ ->
Looking at the response-time specs of the FOD617D,
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I do see one possible issue, namely the rail-rail current through transistors A and B, as one turns off and the other turns on. This can last several us, and partially discharge C. If C = 0.1uF, and we allow a 2-volt drop, then we can handle a 20mA shoot-through current for 0.1*2/0.02 = 10us. OK, that isn't too bad, but let's increase C to 0.22uF to give us more safety margin. That's easier than providing 20us turn-on delays, etc., in the TTL- logic cmos-inverter network, which is a commonly- employed solution to this issue.
Here's the modified new circuit.
floating MOSFET driver, JL, WH Dec07
,-----+----------, _____|_ | | in, 75V max +5 | + | | A |/ (o) ---| | | -> | | | PVI | _|_ |\\v |--' ,--| 1050 | --- C | | \\_/ ->
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