How to make a super fast sampling head?

I was also thinking about just feeding the signal into a fast logic IC, and offset shifting the input with a DAC output, so over many cycles and different values of the DAC I can reconstruct the signal

But that requires 256 samples per point (for 8 bit) multiplied by the time resolution (number of samples in the time domain), so that could amount to long acquisition time for a complete signal

Cheers

Klaus

He might be able to get away with using a SERDES input to an FPGA (etc), which would remove the number of samples in the time domain from the equation.

The only thing I've ever found on the net w.r.t sampling heads was:

sampling.pdf TEK Sampling Oscilloscope Techniques (basic) an47fa.pdf High Speed Amplifier Techniques (Jim Williams) there's a sampling bridge in there somewhere... Tektronix "Sampling Notes" Circuits_1GHz-samplig-Oscilloscope-Front-End.pdf (Robert Houtmann) Looks like it's from a magazine. contains a complete schematic.

(but most of it is pretty old)

Some years ago, I did some analysis of the Tektronix S-6 sampler that may serve as a source of inspiration. This thing has a 30ps rise time.

See .

The sampling pulse is generated using a step-recovery diode and a shorted stub transmission line.

Jeroen Belleman

I suspect that is basically what this one on kickstarter did:

I believe he used Hittite comparators at the input.

You may be able to speed up acquisition a lot by guessing the DAC code for one timepoint on the waveform, based on the DAC code that you found for the previous timepoint on the waveform. You'd just have to check 2 DAC codes for a timepoint if you guess right. If it is above one and below the other then you got it.

On the other hand, I suspect that with noise and jitter, it might be more a matter of finding the DAC code that gives a 50% probability of the comparator output being high, which might slow things down much more. If you spend a really long time you could even characterise the probability of the comparator output being high vs. DAC code, for each timepoint.

Right. You can use a d-flop as a 1-bit sampler. The differential-D ECL parts are expensive but blinding fast. You could use a 15 cent Tiny CMOS flop to get to your speed.

The feedback algorithm can be linear per shot, so it becomes slew-rate limited in the equivalent-time domain. That's easier and less noisy than a binary search. There is some delta-sigma algo that might be better.

I actually have a pcb layout for a very fast 1-bit TDR/sampler, but I haven't had time to set it up and play with it.

A full-bridge or better yet 2-diode half-bridge sampler isn't hard. Typically one closes a diode bias feedback loop so the circuit is sampling the difference from the last sample. I did that with an SRD sample generator and got 70 pS, about 5 GHz bandwidth.

At 500 ps, you could make a series switch s/h with a phemt, SAV551 maybe.

I've experimented with fast bus-switch type analog mux's. Their signal paths are screaming fast, but their switch controls are slow and have gobs of charge injection. Useless.

Certain barbarians here have done 1-diode Lumatron type samplers, which Tektronix gave up after the type N plugin and HP never bothered with. LeCroy later gave that up with shock line technology.

Here's Mark Kahr's great paper on sampling history.

and a Tek thing

Right. Use a tracking algorithm; jog the feedback based on the last, or maybe last two, binary decisions.

Nice set of links

I need to reserve some time to dig into it. Plenty of uses for a high speed S/H, where others would use a brute force GSa ADC.

Cheers

Klaus

Sampling is fascinating and addictive. But cheap ADCs can have insanely fast internal s/h circuits.

People used to sell integrated s/h circuits, not so many now.

Some of the Tiny flip-flops have couple-hundred-ps output edges on Q and Qbar. The pair could drive a full-bridge diode s/h. Maybe $1 or so total.

A flop is about the only way to get a nicely time aligned complementary logic pair. Possibly use a pair of 1 ns Tiny xor gates.

Isn't it a problem that the pull-up and pull-down are slightly different Tpd and strength?

Why not a 1:1:1 transformer?

Clifford Heath.

Concept is trivial, but the devil is in the details. For equivalent time sampling, you need a VERY STABLE signal. You need a DEAD-ON trigger repeatability. You need to be able to slew the delay between trigger and sample a very tiny fraction of the period with HIGH accuracy. Doesn't take much noise to blow all that out of the water.

If all you ever want to do is TDR, it becomes much simpler, but still not trivial.

Start with that and convert some of the ancient technology to current stuff. But much of the magic is in the analog parts. You don't hear much about blowby compensation, but you'll likely need it.

Nowadays, an analog ramp timebase isn't hard. Trigger hits a flop that releases an RC ramp, which drives a comparator working against a DAC to set the delay. You can do the whole thing, except the DAC delay setter, for about a dollar. With just a little care, the RMS jitter can be 1/10000 of the ramp time; 1/50000 if you are more careful.

Triggered, long-duration, low jitter time bases are a project, as in 1 part in 1e9 jitter. Or 1e12.

TDR has the advantage that your own local clock is the trigger, so you can get the big chunks of delay by just counting clock ticks.

One thing you can do nowadays is digitally process fast but ugly step responses to make faster and beautiful step responses. It's a lot easier to make an ugly sampler or TDR than a pretty one.

Klaus - take a look at Electronic Design, Sept 18 2000. The article in "Ideas for Design", "1-Ghz Sampling Oscilloscope Front end is easily modified" shows a couble diode swithches setup as a sampler. A couple text quotes if the titles don't work: "adjustable from 1 to 50 ns/div." and "circuit by switching the two Schottky".

Hul

snipped-for-privacy@gmail.com wrote:

That is a very nice reference.

I had some trouble finding it, links were broken on Electronic Design, but found somebody that had saved it as a PDF:

Then I found a lot of info on this page:

Misc info here from another guy:

A 150ps pulse widht circuit, extremely simple, for TDR generation and sampling:

Explanation here:

Cheers

Klaus

Take a look at the TI ONET1xxx laser drivers. Cheap and really fast.

Cheers

Phil Hobbs

Of course the data sheets assume telecom applications, namely an ac-coupled, dc-balanced data stream. We're trying to figure if they can be used DC-coupled.

Am 13.04.19 um 00:19 schrieb John Larkin:

... and telecom usually ignores the bottom 12 KHz for jitter. Life is easy without 1/f.

cheers, Gerhard

So, I am plying a little with the sampler from this article i Pspice:

It can track a signal resonable, but when the 1ns comparator turns the sample head on (first quad diodes), som charge spills through giving an incorrect amplitude

It's worse when the sampler turns off, on a 1V signal, the amplitude is 100mV off. I am using a small capacitor of 20pF to hold the signal, but the charge transfer from the 2pF shunt capacitance of the diode versus this 20pF cap is too high

If I increase the cap, it's nowhere near a 1GHz sampler, if I decrease it, it has very low hold time

I do not have the 15MOhm/1MOhm - 1pF/15pF (internal cap of TL082) combination, but perhaps I should??

Cheers

Klaus