how to get ground referenced amplified V difference from high side (250VDC) shunt?

Michael · 2007-12-08T03:59:47+00:00

Hi - I want to put a high side shunt resistor on a grounded load(~10ma peak) that has about 250VDC across it. I then want to have aground referenced voltage that is the amplified difference across theshunt with a range of about 0-5V. I would like the voltage across theshunt to be in the low mV range. Power supplies available to me willbe the 250V, which will be noisy, 5V, and probably some sort of +-12Vanalog (clean) supply. I would like to get 8b or more of resolutionfrom the ground referenced amplified shunt voltage signal. I wouldalso like this circuit to be fast. The faster the better, MHzbandwidth at least. If this were a lower voltage I'd just do an op-ampdifference amplifier. Unfortunately, last I checked, Apex had themarket for op-amps that can handle such high voltages fairly wellcornered, and their op-amps are expensive, large, and not particularlyquick. High side current amplifiers seem to top out at about 100VDC.So I'm trying out various ideas. My favorite right now is to putvoltage dividers on both sides of the shunt to drop the voltage downmaybe to 0-10V on both and then use an instrumentation amplifier toamplify that voltage. For some odd reason this bothers me, but I can'tplace my finger on just why.Am I being paranoid and the instrumentation amp is a legitimate idea,or is there a better way to do this?Thanks!-Michael

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Jonathan Kirwan 18 years ago

I enjoyed looking this one over and learned from it. But I have a few questions.

First, since Q5 nominally needs to split away Ib/2 and its beta is on the order of 1% or so (maybe 1/2%, but you get the idea), the base of Q5 will have to rob some current from the collector of Q4. That current cannot then proceed through the Q1/Q2 mirror. And, I'd guess, this ultimately will account for a noticeable error at the output (no, I didn't try to work out the exact amount, but I'm guessing it will be in the area of maybe 1-5% by itself?) That will add to Q1/Q2 and Q3/Q4 matching errors. Why didn't you choose to make it Darlington to nearly eliminate that error?

Ib is in the area of about 1mA (a little less, figuring roughly 2.5V on the bottom side and 5-6V on the pair of mirrors side, leaving most of the rest of 250V, maybe 242V or so, across it.) Okay. So 900uA or so. This sets up about 450uA on each side of the mirror paths. You've chosen 10 ohms for Rs, for a change of 0-100mV over the range of a

0-10mA load. I understand that R1 can also be seen as two parallel (Rs+R2) resistors, once for each of the two equal currents that proceed through Q1 and Q5 when there is no load present. But you decided on 190 ohms for R2. It turns out that 450uA is one part in 20 of 10mA and that this is also roughly the ratio of Rs to (Rs+R2). So I think I understand this relationship. But what caused you to set the 200 ohm emitter leg resistor magnitude in the first place? In other words, suppose I set Rs to 20 ohms, R2 to 380 ohms and R1 to 200? I think the output would still range over the 0-5V desired output over the same load current range. The only difference is that the load would see another tenth volt drop at max load. What was your thinking for the 200 ohm magnitude, itself?

You set R3 and R4 to 10k. They will yield about a 5V drop (4.5V?). Is the magnitude of this based upon the tiny (26mV/Ie-in-mA) re, large enough to greatly overwhelm it? Or some other reasoning?

Thanks, Jon

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Electroniker 18 years ago

Nice ASCII art. Can the original poster reveal how this was composed?

--- Blakely LaCroix Minneapolis, Minnesota, USA

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JeffM 18 years ago

All that is required is a text editor with a monospaced font.

This make things easier:

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*+*-*-*-*-great-job+Andy's-ASCII-Circuit

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Jonathan Kirwan 18 years ago

I use a short program I wrote. Source is available on my site, but this link will get you four files:

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They are the ASC.COM and ASC.SYM files (must run in a DOS box) that I use; plus HV.ASC, which is an LTSpice schematic example of Winfield's circuit, and HV.TXT, which is the automated output from ASC.COM. This allows you to use LTSpice (a free simulator, with schematic capture, program from linear.com) to capture the schematic and save it and then run ASC.COM on it to generate output that you can direct to a file and load with notepad, etc.

There is also

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, which provides an ASCII schematic editor called AACircuit. That avoids LTSpice and lets you directly enter schematics using a specialized editor. I prefer being able to place my schematics into LTSpice, though. Which is why I wrote that program to convert. What I wrote is not a panacea, though, and it cannot handle all forms of LTSpice schematics. But it handles simpler ones.

If you get my zip file from above, here's the output that was automatically generated from the schematic included there:

As you can see, it's serviceable for some things.

Jon

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Jonathan Kirwan 18 years ago

I updated this, so that the schematic looks much closer to Winfield's. That link above now has the newer, closer version.

The older version is now:

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Jon

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Winfield Hill 18 years ago

I'm glad you enjoyed it, so did I.

Yes, I thought of that, but my ASCII drawing energy was running low, and the drawing was getting cluttered, so I rationalized using the datasheet's typical beta = 150 plot (even tho I know that high-voltage transistors do suffer in this regard), for a hopeful under 1% error. So yes, anyway, do make Q5 a Darlington if you like.

The OP wanted a low measurement voltage drop, and so I picked (or he picked?) 100mV as a conmpromise. Then I aimed for 1/2 mA (getting 450uA, as you calculated) for the zero-signal bias current, to insure a more than 1MHz bandwidth. Then I picked 1mA for the full-scale output signal current, less could reduce accuracy (compare to the quiescent level) and more could mean too much power dissipation in Q5, which was dropping nearly 250V (this was before I added the 100k 0.5W collector resistor).

That's it, in part, but mostly I was worried about the offset voltages for the pair of "matched" transistors.

As Jim commented, offset voltages and matching are a big deal in circuits like this (especially if they are not made with ICs), and in reality the Q1 Q2 mismatch is a painful problem. Along with 1% resistor errors it means there'll be an output zero-error voltage to trim away, and it can also mean that some of the Ib current won't cancel out, leaving an error that's proportional to the 250V supply, requiring a second trim on the Ib path.

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Winfield Hill 18 years ago

By hand, in notepad. I've done hundreds of them here on s.e.d. over the years. It really doesn't take long once you get used to it. Also, I prefer the tight drawings I can make by hand, compared to computer-program assistants.

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Jonathan Kirwan 18 years ago

Occasional gems like this make the rest of the panning worthwhile.

Thanks. I though it seemed important for that reason.

There is another thought that comes to mind, but perhaps more from my hobbyist ignorance about these things. The Q5 collector current varies from 450uA to 1450uA, or so. A span of 1mA, set by Rs/R1 times the 10mA max load current. This means that Q5's Vce swings around, now, since instead of nailing the collector to the virtual ground you've inserted the 100k to share some of the Vce and dissipation. Wouldn't that mean not only is there an effect due to siphoning off needed base current from the mirror path, but yet another to the Early effect, yielding an additional effect due to beta variation? With this kind of Vce variation, not so far from the VA of the device, my memory nags at me that the beta does vary enough to think about here.

I noted the 100k collector resistor and gathered that purpose. With the collector moving around like that because of the 100k, though, doesn't it then impact the frequency response? For frequency response reasons, wouldn't it be better to just nail the collector down?

Ah. I missed that detail. I think I see what you mean. I'll look more closely.

I see those two points, well. Thanks.

Jon

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Winfield 18 years ago

No serious effect from V_A -- that changes Vbe a little bit, yes, but it's inside a feedback loop and simply changes the voltage on Q4's collector a little bit.

That's a good point, even though Ccb for a mpsA92 is only about 1.2pF (for Vce above 25V) the G=1000 ac stage gain! will cause mucho trouble. For my spice tests I added 100pF in parallel with the 100k, speeding up the response to 5MHz (compared to 80kHz without the cap) and 40ns rise/falltime.

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Jonathan Kirwan 18 years ago

I was thinking not in those terms, though it did cross my mind and I tossed it out for the same reasons you just mentioned. It was just that I imagined about impact on beta, not Vbe. Now that I think more on what I remember, (1+Vce/VA)*beta (though that could be a completely faulty lark of memory), even that wouldn't be all that important. The beta would be at least as good, and get better, not worse. So never mind. In short, I've dropped it out of any thoughts.

A speed-up cap. I should have figured on my own. Thanks.

Jon

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