How to design a simplest trigger circuit

I might have misunderstood... I thought the OP was just looking for a trigger cct for some external edge triggered device. But yeah... if it was like that ...it's not known if the FF is toggling right.

D from BC

No, I simply didn't draw as well as you, and the name of the physical gate you use is still a NAND gate, one of the four NANDs in a package, as you very well know. What we should have told deepak, is these gates should be Schmitt-trigger types, which includes the inverter (INV) acting on the output of the R-C delay (make from the 4th NAND). E.g., a cmos cd4093 or a 74hc132 could be used. He'll use one quad NAND package and an inverter, with five unuder gates... Maybe they're other things he can do with the left-overs.

deepak's scheme doesn't look good to me, e.g., how does the destination get synchronized so a HI input means the output is ON, etc.? And if it is synchronized, any little noise pulse can unsync it. It'd be better to use the two low- going pulses generated separately, ON and OFF, somehow, such as into a flip flop. But then, why bother, you already have an ON-OFF signal.

Maybe deepak can tell us what he's doing?

Sounds like a transistor or triac will work fine for this application.

If we can create a delayed sqr pulse as shown below +---------------------------+ | |

--------+ +-------------- --------+ +------------- | | +----------------------------+

-------+ +-------------------------+ +------

and use this circuit (see in courier font)

The three inverter circuit ( >o ) creates appropriate delay between the inputs. May be we can get the desired response. Any comments.

On Thu, 22 Nov 2007 10:49:19 -0800 (PST), Winfield wrote:

--- Yes, of course it has to be a NAND:

Version 4 SHEET 1 880 680 WIRE -48 128 -384 128 WIRE 80 128 16 128 WIRE 192 176 144 176 WIRE 80 192 -112 192 WIRE 192 208 192 176 WIRE 256 208 192 208 WIRE 352 256 320 256 WIRE 256 272 192 272 WIRE -384 288 -384 128 WIRE -240 288 -384 288 WIRE -128 288 -160 288 WIRE -112 288 -112 192 WIRE -112 288 -128 288 WIRE -48 288 -112 288 WIRE 80 288 16 288 WIRE 192 304 192 272 WIRE 192 304 144 304 WIRE 352 336 352 256 WIRE -384 352 -384 288 WIRE 80 352 -384 352 WIRE -384 384 -384 352 WIRE -128 400 -128 288 WIRE -384 496 -384 464 WIRE -128 496 -128 464 WIRE -128 496 -384 496 WIRE 352 496 352 416 WIRE 352 496 -128 496 WIRE -384 544 -384 496 FLAG -384 544 0 SYMBOL Digital\\\\and 112 96 R0 WINDOW 3 16 52 Invisible 0 SYMATTR InstName A1 SYMATTR Value vhigh 5v trise 10e-9 tfall 10e-9 SYMBOL res -144 272 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL Digital\\\\inv -48 64 R0 WINDOW 3 0 0 Invisible 0 SYMATTR InstName A4 SYMATTR Value vhigh 5v trise 10e-9 tfall 10e-9 SYMBOL voltage -384 368 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 5 0 1e-6 1e-6 1e-3 2e-3) SYMBOL cap -144 400 R0 SYMATTR InstName C1 SYMATTR Value 1e-9 SYMBOL Digital\\\\and 288 176 R0 WINDOW 3 16 52 Invisible 0 SYMATTR InstName A3 SYMATTR Value vhigh 5v trise 10e-9 tfall 10e-9 SYMBOL Digital\\\\and 112 384 M180 WINDOW 3 16 52 Invisible 0 SYMATTR InstName A2 SYMATTR Value vhigh 5v trise 10e-9 tfall 10e-9 SYMBOL Digital\\\\inv -48 224 R0 WINDOW 3 0 0 Invisible 0 SYMATTR InstName A5 SYMATTR Value vhigh 5v trise 10e-9 tfall 10e-9 SYMBOL res 336 320 R0 SYMATTR InstName R2 SYMATTR Value 10k TEXT -360 520 Left 0 !.tran 10e-3

and my point was that you used the wrong symbol for a NAND when, clearly, you used the right symbol for the other two.

Since it's either of the low-going pulses which gets inverted in the output NAND, it appears you were trying to use De Morgan notation but got it wrong.

No big deal, I was just pointing out your error by showing you the proper notation.

---

--- From a previous post, like this:

---

--- Yes.

As I suggested in my original post:

--- I'm beginning to have my doubts. ;)

-- JF