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How to bias a CS mosfet, a different approach

Version 4 SHEET 1 884 680 WIRE 176 64 80 64 WIRE 304 64 176 64 WIRE 496 64 400 64 WIRE 592 64 496 64 WIRE 752 64 672 64 WIRE 176 96 176 64 WIRE 496 96 496 64 WIRE 752 128 752 64 WIRE 176 208 176 176 WIRE 352 208 352 128 WIRE 352 208 176 208 WIRE 496 208 496 176 WIRE 640 208 496 208 WIRE 704 208 640 208 WIRE 640 224 640 208 WIRE 80 304 80 64 WIRE 176 304 176 208 WIRE 496 304 496 208 WIRE 640 304 640 288 WIRE 80 416 80 384 WIRE 176 416 176 384 WIRE 176 416 80 416 WIRE 496 416 496 384 WIRE 496 416 176 416 WIRE 640 416 640 384 WIRE 640 416 496 416 WIRE 752 416 752 224 WIRE 752 416 640 416 WIRE 80 480 80 416 FLAG 80 480 0 FLAG 80 64 Vcc FLAG 496 64 Vcc/2 SYMBOL res 160 80 R0 SYMATTR InstName R1 SYMATTR Value 1000 SYMBOL res 160 288 R0 SYMATTR InstName R2 SYMATTR Value 1100 SYMBOL npn 304 128 R270 SYMATTR InstName Q1 SYMATTR Value ZTX1048A SYMBOL res 480 80 R0 SYMATTR InstName R3 SYMATTR Value 1000 SYMBOL voltage 80 288 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 30 0 .1) SYMBOL res 480 288 R0 SYMATTR InstName R4 SYMATTR Value 1000 SYMBOL nmos 704 128 R0 SYMATTR InstName M1 SYMATTR Value IRF1312S SYMBOL res 688 48 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R5 SYMATTR Value 100 SYMBOL voltage 640 288 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value SINE(0 .25 1000) SYMBOL cap 624 224 R0 WINDOW 0 -42 6 Left 0 WINDOW 3 -36 38 Left 0 SYMATTR InstName C1 SYMATTR Value 10µ TEXT 88 448 Left 0 !.tran .1

--
JF
Reply to
John Fields
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I'm sure Jim Thompson will approve.

John

Reply to
John Larkin 

--
If he sees nothing wrong with it, I'm sure he'll be at least neutral.
If he sees something wrong with it I expect he'll comment on it, we'll
discuss the issue(s) like rational adults, do what needs to be done to
resolve the issues, and get on with our lives.
Reply to
John Fields

Well, let's just wait for his objective, professional comments.

John

Reply to
John Larkin 

--
Yeah, right. 

Seems to me like you're waiting around like a rabid dog.
Reply to
John Fields

There seems to be AC output only when ~11V = 12V.

Is this intended?

John S

Reply to
John S

The question is: will Jim actively or passively approve of your circuit?

John

Reply to
John Larkin

[snip already downloaded]

Where's the 555 ?:-) ...Jim Thompson

[On the Road, in New York] 
--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

--- No.

It's a consequence of the circuit and is caused by the gate bias voltage developed by R3 and R4 forcing the MOSFET to transition between cutoff and saturation, coupled with the effect of the AC input between those points.

The location of the transition region will vary, with respect to Vcc/2, as a function of the ratio of R3:R4, and will approach Vcc2 as R3/R4 -> infinity.

That seems to me to be what the OP was asking for: a source of Vcc/2 for a drain supply, a divider from Vcc/2 to ground to set the bias of the DUT, and a source of AC to exercise the load.

-- JF

Reply to
John Fields

On 8/16/2011 8:05 PM, John Fields wrote:

Okay. Then I think we are having difficulty understanding what the OP wants. I interpreted his specs such that the following gives what he wanted (display V(d)):

Version 4 SHEET 1 1264 680 WIRE 32 -336 -240 -336 WIRE 208 -336 32 -336 WIRE 288 -336 208 -336 WIRE 368 -336 288 -336 WIRE -240 -304 -240 -336 WIRE 32 -240 32 -336 WIRE 208 -240 208 -336 WIRE 368 -240 368 -336 WIRE -240 -192 -240 -224 WIRE -144 -144 -176 -144 WIRE 208 -144 208 -160 WIRE 368 -144 368 -160 WIRE 32 -112 32 -176 WIRE 32 -112 16 -112 WIRE 80 -112 32 -112 WIRE 208 -112 208 -144 WIRE 208 -112 160 -112 WIRE -352 -64 -400 -64 WIRE -240 -64 -240 -96 WIRE -240 -64 -288 -64 WIRE -144 -64 -144 -144 WIRE -144 -64 -240 -64 WIRE -48 -64 -144 -64 WIRE -400 0 -400 -64 WIRE -240 48 -240 -64 WIRE 208 64 208 -112 WIRE -240 144 -240 128 WIRE 16 144 16 -16 WIRE 32 144 16 144 WIRE 144 144 112 144 WIRE 160 144 144 144 WIRE 432 160 208 160 WIRE 656 160 512 160 WIRE 656 192 656 160 WIRE 16 224 16 144 WIRE 144 224 144 144 WIRE 240 224 144 224 WIRE 432 224 304 224 WIRE 512 224 432 224 WIRE 512 256 512 224 WIRE 16 320 16 304 WIRE 512 352 512 336 FLAG -240 144 0 FLAG 368 -144 0 FLAG 656 192 0 FLAG 288 -336 dd FLAG 208 -144 d FLAG 16 320 0 FLAG 432 224 in FLAG 512 352 0 FLAG -400 0 0 SYMBOL nmos 160 64 R0 SYMATTR InstName M1 SYMATTR Value BSZ0920NS SYMBOL res 192 -256 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL voltage 368 -256 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL pnp -48 -16 M180 WINDOW 0 35 48 Left 0 WINDOW 3 -50 101 Left 0 SYMATTR InstName Q1 SYMATTR Value 2N3906 SYMBOL res -256 -320 R0 SYMATTR InstName R2 SYMATTR Value 12k SYMBOL res -256 32 R0 SYMATTR InstName R3 SYMATTR Value 10.4k SYMBOL res 0 208 R0 SYMATTR InstName R4 SYMATTR Value 1Meg SYMBOL cap 304 208 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C2 SYMATTR Value 10µ SYMBOL voltage 512 240 R0 WINDOW 123 24 132 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value2 AC .001 SYMATTR InstName V2 SYMATTR Value SINE(0 1m 1k) SYMBOL cap -288 -80 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C3 SYMATTR Value 470µ SYMBOL res 16 160 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R5 SYMATTR Value 1Meg SYMBOL res 64 -96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R6 SYMATTR Value 100k SYMBOL cap 16 -240 R0 SYMATTR InstName C1 SYMATTR Value 470µ SYMBOL res 416 176 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R7 SYMATTR Value 3.5 SYMBOL pnp -176 -96 R180 WINDOW 0 35 48 Left 0 WINDOW 3 -50 101 Left 0 SYMATTR InstName Q2 SYMATTR Value 2N3906 TEXT -664 -144 Left 0 !;dc v1 10.8 13.2 .001 TEXT 608 -176 Left 0 ;100*(V(d)-.5*v(dd))/v(dd) TEXT 600 -216 Left 0 ;Put this into the DC Sweep trace window to see %error: TEXT -664 -72 Left 0 !.tran 0 .5 1m TEXT -664 -112 Left 0 !;ac dec 100k 20 20000 TEXT -664 96 Left 0 !.step v1 list 10 12 14

John S

Reply to
John S 

--
Everywhere!
Reply to
John Fields

Yes, I think that's what he meant.

But as long as you have the two PNP transistors, why not make a diffamp? The numbers are much better.

ftp://jjlarkin.lmi.net/Bias_Servo.jpg

John

Reply to
John Larkin

(snip LTSpice schematic)

I don't disagree. Would you please modify the LTSpice and post it here?

John S

Reply to
John S

No thanks.

John

Reply to
John Larkin 

--
By "passive approval" you mean that if he doesn't respond negatively
he will have approved and you'll have placed him in a box.

What a scoundrel you are!

The real question is: What difference does it make, either way?

The answer is: It doesn't, and your amateurish attempt at getting him
to commit, on your say-so, to either way, is just another instance of
your insatiable need to control and manipulate.
Reply to
John Fields 

--

I agree.
Reply to
John Fields 

--
Right next to the PIC. ;)
Reply to
John Fields

Just having a little fun. Does he defend his buddy's absurd circuit? Does he continue to pretend to killfile me? It's a great personal/professional dilemma. I think he'll chicken out and say nothing.

John

Reply to
John Larkin 

--
As always, at someone else's expense.
Reply to
John Fields

Well, at the expense of a couple of profane, sour old gits. Who can't bias mosfets.

John

Reply to
John Larkin

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