I want an array of 0.5-1 A current sources to drive an array of laser diodes from a 3 V battery. The laser packages all have case anodes. I used an op amp (TI TLV2761) to drive the base on a n-channel MOSFET (Phillip PSMN006_20K) with the diode on it's drain and a 0.1 ohm sense resistor from source to ground. The op amp has a 1k resistor between the output and the FET base. The negative input to the op amp is sensing the resistor voltage and the positive input is used to set the sense resistor voltage, and thus the current. This is a common textbook circuit, refer to Tietze & Schenk Fig. 13.11b or AofE fig
4.12 (but w/out the bjt part).
I have nearly 100% current modulation at about 30 kHz! I thought it was a ground problem, but soldering ground right to the sense resistor didn't help. Changing the op amp output resistor to 10 k changes the frequency to about 13 kHz.
Could anyone advise how I might best quench this unintended oscillator?
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G
geoff.fanning
I want an array of 0.5-1 A current sources to drive an array of laser diodes from a 3 V battery. The laser packages all have case anodes. I used an op amp (TI TLV2761) to drive the base on a n-channel MOSFET (Phillip PSMN006_20K) with the diode on it's drain and a 0.1 ohm sense resistor from source to ground. The op amp has a 1k resistor between the output and the FET base. The negative input to the op amp is sensing the resistor voltage and the positive input is used to set the sense resistor voltage, and thus the current. This is a common textbook circuit, refer to Tietze & Schenk Fig. 13.11b or AofE fig
4.12 (but w/out the bjt part).
I have nearly 100% current modulation at about 30 kHz! I thought it was a ground problem, but soldering ground right to the sense resistor didn't help. Changing the op amp output resistor to 10 k changes the frequency to about 13 kHz.
Could anyone advise how I might best quench this unintended oscillator?
J
Joerg
4.12 looks a bit different, has a BJT for the load current.
Can you post a schematic? The R and the FET's Cgs provide a delay and if you tap off for feedback at the sense resistor you may have made the loop unstable. Increasing R will reduce the frequency if it oscillates. This FET is >4000pF Vgs and the oscillation frequency corroborates that pretty well for the 10k case. For the 1k case there are probably other delays added in, opamp having a hard time etc.
You could add a cap from In- to OUT on the opamps. If you need to modulate the laser diodes you'll have to drive these FETs much harder.
BTW, make sure you know what happens during power-up. Laser diodes can die after nanoseconds of over-current.
Regards, Joerg
http://www.analogconsultants.com
T
Tim Wescott
This is what I was going to suggest. I'm also wondering why you feel you need such a large resistor to the FET gate. _Decreasing_ this resistance will make everything faster, at the cost of loading the op amp more heavily if you need to slew the laser current fast. My gut feel for a jelly-bean op-amp is 100 ohms or so, although 500-600 is probably safest (assuming the proper compensation cap).
This should be the sort of thing that's very amenable to SPICE analysis. If I were doing this (and I had a good model of the FET) I'd check out it's behavior with LTSpice.
Tim Wescott
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J
John Larkin
in-------------opamp+
out ------+-------r-------gate +----opamp- | 47r | c | | +------------------------+-------r-----------source | | 0.1r r | gnd
John
C
Chris Jones
The Rout of the op-amp (plus the 1k resistor) and the Cgs of the FET form a pole that gives phase shift, and there is another pole inside the op-amp (the on-chip compensation cap), so these two poles give almost 90 degrees of phase shift each, and together with a few extra degrees from some other part of the op-amp, that brings you up to the total of 180 degrees, turning your negative feedback into positive feedback at some frequency.
First try shorting the 1k resistor and put in the beefiest op-amp (lowest open loop Rout) that you can find. Also swap out the FET for the smallest (lowest Cgs) model that you can find. This might push out the opamp_rout * FET_Cgs pole far enough to get it stable, though I would then throroughly test the step response for ringing before I would trust it to stay quiet. It'd probably be worth testing with different step amplitudes and at high and low temperatures and supply voltages too because it'll be hard to push that pole out far enough to get it really stable.
You could try getting rid of one pole, by replacing the op-amp with an OTA, e.g. LM13700. That way, the Cgs of the FET is the compensation cap, and there is no significant pole inside the OTA. Unfortunately, I think the LM13700 won't work from your 3V battery. It would be nice if there were a single-supply CMOS rail-to-rail-output OTA with inputs that work down to the negative rail, but I don't know of one. Unfortunately, there don't seem to be many different OTAs on the market, even though this is a very common circuit on ASICs. I think the problem is that not many electronic engineers other than chip designers know how useful an OTA would be or even what it is, and so they don't ask for one, and chip companies don't hear anyone asking for OTAs so they don't bother to offer them, even though they use plenty inside custom chips.
If you can't get a suitable OTA, then you could also try to make the pole with the FET gate capacitance and the op-amp output resistance become dominant, but this will involve slowing everything down so the response time will be awful. You could put deliberate series resistance (many kOhm) between the op-amp output and the FET gate, and hang an extra capacitor between the gate and ground, and also provide some resistive feedback around the op-amp to make its pole introduce less phase shift between the current sense resistor and the output of the op-amp. As another poster mentioned, this kind of problem should really be simulated. Try looking at the step response when you think you've finished, and look for ringing.
Chris
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