For narrow (fdev ~ 0.05 %) FM detection the phase noise of the CD74HCT4046 PLL's VCO causes poor S+N/N ratio. Has a smaller / larger oscillator C any influence and also the values of R1 and R2 of the VCO. Do the 74HC(T)7046 or 74HC(T)9046 perform any better?
6 e
Probably not. My - educated - guess is that the noise comes from the MOS transistors in the oscillator, causing the random shifts in the timing between successive transitions.
The only useful way of reducing this noise is to run the VCO faster and use a counter to divide the output frequency down to actual frequency that you need.
The phase noise is still there, but it is reduced in proportion to the divide ratio, because the voltage noise in the transistors is unchanged but the voltage ramp that is driving the switching is steeper in proportion to the divide ratio.
-- Bill Sloman, Nijmegen
What percentage of the fmax-fmin range is your FM signal covering? Or, asking the same in a different way, what is your VCO control voltage swing?
Pere
On Jun 17, 3:11 pm, Bill Sloman
I didn't expect that. Nice one, thanks for this trick.
3dB improvement in S/N per divide by 2? M
6 dB. Phase is like amplitude.
To the OP:
[Obligatory 7 AM rant: the HC versions of the 4046 are quicker, but whoever designed it did a rotten job. The oscillator in the metal gate version is good for 1000:1 frequency range, but the HC one quits when the control voltage is below about VDD/10. Pathetic.]However, the leading possibility for the origin of your nasty phase noise is the dead band in the phase-frequency detector (PD II, I think). If you're using that one, try sticking a large value resistor from the PD output to ground to pull it out of the dead band--your phase noise should improve remarkably.
If that isn't it, there are a few possibilities, one of which is frequency division as Bill suggested.
Besides that, you could run an offset loop by mixing the oscillator output with a crystal-controlled clock, and running the PD at the difference frequency. If the VCO range is too wide, and the phase detector is symmetrical (e.g. an XOR) you can lock up on the wrong sideband. Either restrict the tuning range (not that easy with a 4046 since the frequency tolerances are so sloppy), or use the phase-frequency detector.
Locking up on the lower sideband requires the phase detector to run 180 degrees instead of 0 (or -90 instead of +90, depending). XORs and diode mixers work fine like that, but PFDs don't--the loop has to try servoing on the big cliff instead of the nice gentle slope. The effective loop gain is different by about 500X, so the loop won't lock there--it'll bounce around until it finds the stable null, which forces it to pick the right sideband.
All that is a lot more work than adding one resistor!
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
You've had all the comments that stay in the box you've jumped into.
Here's mine:
Just use an LC oscillator! Unless you work hard to screw it up, the phase noise is going to be miles lower than anything you can do with a multivibrator.
If oscillators were hammers, most multivibrators would make very nice rocks. Sometimes that's all you need.
-- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Plan B was a quadrature detector which works with LC phase shifter where S+N/N is proportional to the Q of the LC. An LC VCO is a good option indeed but then a 74HCT4046 for just an EXOR is not. A small signal multiplier could be driven directly by a colpitts. I'll try this first, and see what it does.
G.Baars
[snip]
Use an ECL/PECL XOR (plus an OpAmp) as an analog PD, as in...
Patent 3,644,835 Phase Detector
(Copy available on my website.) ...Jim Thompson
--
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The only thing bipartisan in this country is hypocrisy
A 4046 will always be noisy here.
Consider buying a narrowband packaged VCO; they cost a few dollars and will have far less phase noise. An XOR phase detector will be nice and linear.
Or consider some other kind of non-PLL FM discriminator, like a high-Q phase shifter (technically a very peaky lowpass filter) and an XOR.
Or heterodyne it low enough to get, say, a 2:1 frequency swing and use a tachometer discriminator.
ftp://jjlarkin.lmi.net/DoubleTach.jpg
John
Sure looks like the right solution for "narrow (fdev ~ 0.05 %) FM detection" :-) ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The only thing bipartisan in this country is hypocrisy
Why not a single gate?
There are others.
-- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Of course it is logical to work with TTL levels in a small signal design. Just set the inputs at Vcc/2 and couple AC don';t you agree.
Can be risky if the device does have Schmitt inputs. Else, if the AC-coupled input signal stops or becomes too slow, a CMOS device biased at VCC/2 can draw a lot of current and also oscillate ... phsss ... *POOF*
Also, logic stuff is going more towards 3.3V supplies these days.
-- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
Well...
TTL levels aren't 0V and 5V -- it's more like 0.2V and 2.7V on the output side. 5V CMOS levels are 0 and 5V, with all sorts of caveats.
Using 0 and 5V _levels_ isn't a bad idea, but if you're concerned about phase noise then trying to use a TTL gate to square up a sine wave could be -- I'd use some good ol' analog circuitry to square things up _then_ run it all through the TTL (or CMOS) gates.
-- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
With the same absolute jitter from the MOS transistors, the VCO noise sidebands will look proportionally worse at the higher frequency, and dividing down will get you where you started if you are lucky. No free lunch here.
In real life you add the phase noise of the frequency divider. If you want low phase noise, you need a resonance with substantial Q.
regards, Gerhard
ns.
The whole point of the exercise is to reduce the absolute jitter in proportion to the divide ratio - the voltage noise in the relevant MOS transistors remains the same, but they are looking at a steeper waveform, so the absolute jitter is reduced.
Wrong.
The phase noise of the frequency divider is a lot less than the phase noise in the VCO - the transisotrs in the frequency divider are looking at much steeper-sided transistions than the transistors in the oscillator. The voltage nose level is roughly the same so the jitter is an order of magnitude or so lower.
-- Bill Sloman, Nijmegen
The OP should really try that high value resistor to ground from the phase detector output, to pull the loop out of the dead zone. It's a lot like an LM324 that way--an ugly bug, uglier at higher frequency, easy to fix.
If it's a problem with the RC VCO, it'll still be a problem with an LC VCO.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
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