o VCC | | |-+ +------+------->| | | |-+ N-FET | | | C =3D=3D=3D | C | C/2 | C | | C +----------+ C | | C | |=AF| C =3D=3D=3D | | | L | C/2 |_| R | | | =3D=3D=3D =3D=3D=3D =3D=3D=3D
If all components were noiseless, this would oscillate at an ideally stable frequency close to 2*pi*f0 =3D 1/(L*C)^(1/2). Some frequency offset will result from the internal capacitances and phase lag of the FET, and harmonics will be introduced by its transfer characteristic. Assume the
tank L/C to be chosen such that the FET is only mildly non-linear, i.e.
that it doesn't turn off completely during a cycle.
In reality, the resistors as well as the FET channel inject a thermal voltage noise of (4*kB*T*R)^(1/2), or alternatively a current noise of (4*kB*T/R)^(1/2). This will cause the oscillator frequency to fluctuate
around f0. If you repeately measure the average frequency over a fixed duration tau, the scatter of your results should decrease with increasing tau, however.
Now my question: is it possible to predict the average frequency offset
for a given tau from the values of the circuit components? I would naively expect the answer to depend on the tank circuit quality factor, so a coil resistance RL might have to be introduced as well. But then, R makes for tank circuit damping too.
If specific data can help, take my test circuit data of L=3D550uH, C=3D11nF, RL=3D2ohm, R=3D1kohm, BF245A (IDSS=3D4mA, VTO=3D-1.7V) for the N-FET, VCC= =3D9V, and tau=3D10sec. (The circuit is temperature-compensated to about 1ppm/deg and packed in styrofoam, where C and L are in good thermal contact.)
I can't help you on the noise calculation, but I can suggest a couple=20 things that will reduce it. The Q of the tuned circuit is key to a=20 low noise oscillator. This implies that replacing the source resistor=20 with something else might help a lot. Some possibilities are an=20 active current source or a large inductor (relative to resonance with=20 the capacitors). A PNP follower between the capacitor tap and the=20 source could use a very high resistance to bias the base close to=20 zero, but a negative collector supply would be needed if you expect=20 much amplitude from the oscillator.
You might also get some improvement with other capacitor ratios than 1:1.=
Unfortunately, this sort of thing is hard to optimize with Spice, for=20 lack of good field effect device models.
Thanks for the comments, John. I am interested in a direct (semi-)quantitative estimate of the frequency noise from scratch, for a minimalist design like this (sophisticated ones can come later). If Spice could help with this, I would be glad.
My f0 is around 60kHz. How many =B5Hz or nHz (?or even less) offset over
ten seconds can one expect? There must be a way to calculate this.
Over 10 seconds, you're going to get a lot of 1/f noise from the fet, plus millikelvin temperature drift effects. The noise spectrum of an oscillator like this gets huge close-in.
Ummm... you're hoping to get that sort of precision and accuracy out of an LC oscillator? A shift of just one clock period (15 microseconds) would be close to one part per million.
I have a feeling that component-value drift in the L and C components, due to temperature changes (room-ambient, oscillator-current heating, etc.) is going to cause frequency shifts quite a lot larger than the sort of voltage-noise problems you're trying to quantify.
Amateur-radio developers who build this sort of oscillator often play quite a few tricks to reduce the temperature sensitivity (e.g. including some caps whose TCO complements the TCO of a powdered- iron-core toroidal inductor) and are still happy to get a circuit which drifts no more than 100 Hz in a half-hour after a prolonged warm-up. That's for an F0 somewhere up in the single-digit MHz range... and they're not trying for absolute accuracy, just for low drift.
Seems to me that you'd want something more along the lines of a temperature-compensated crystal oscillator (or even an ovenized one) followed by a divider.
Or, am I missing something?
--
Dave Platt AE6EO
Hosting the Jade Warrior home page: http://www.radagast.org/jade-warrior
I do _not_ wish to receive unsolicited commercial email, and I will
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Actually we did better than 100Hz. But this required a large box, a hefty amount of styrofoam and a good temp control loop. I'd never do that again today after learning how dangerous styrofoam can become when something burns up in there. A whole other matter was linear tuning. If you didn't want to do the mechanics for a moving core you sat there for hours bending the fins of a variable capacitor.
On another note I never had much luck with FETs such as the BF245A that Martin is using. I used BJTs, the equivalent of what now would be a BFS17. Well, sometimes it was still GE transistors.
Many thanks for the comments made so far, concerning an estimation of the frequency noise for this circuit (capacitance labels corrected):
John Lark>
The 1/f noise from channel surface defects (?) is a low-frequency affair; for most small-signal J-FETs it dissapears into the white channel noise
around 1kHz or 10kHz - below my f0 of 60kHz. So the question is: to what extent does low-frequency noise modulate f0? Judging from the dependence of f0 on supply voltage (1ppm from VCC=3D8 to 10V) this effect should be very small. Could it still be more important than white noise from the vicinity of f0?
Did I notice the millikelvin drift effects! With temperature coefficients around +200ppm/deg for my L and -200ppm/deg for my C, a 1mK differential means a frequency shift of 1*10^-7. However, these effects were the result of erratic air convection and have been dealt with by styrofoam encapsulation with good thermal contact between L and C. (BTW, I think intrinsic thermodynamic temperature fluctuations can be neglected for
10^23 or so atoms.)
Dave Platt wrote:
Errrhhh, the order-of-magnitude numbers were just to express my ignorance: I hoped they might induce someone to come up with a calculation. They are by no means a design goal. (Actually, I do have some suspicion where the true frequency-noise level of this oscillator is.)
Yes, the oscillator dissipates about 10mW, and the temperature differential resulting from the heat flow manifests itself in a turn-on drift. I have compensated the temperature coefficients to about 1ppm/deg; this should
make ambient temperature variations unnoticeable over observational periods of 10 seconds.
BTW, never use polystyrene caps for temperature compensation: their variation from moisture uptake can easily exceed their variation with temperature between the Antarctic and the Sahara! Use polypropylene instead.
Just take me for a curious guy: I simply want to know how to estimate the frequency noise of this oscillator, i.e. what the general principles are, and what the dominant mechanism is. The example oscillator could be replaced by a BJT and/or crystal circuit if this would help make the task easier!
Joerg wrote:
Yes, one can do better. A drift below +/-100Hz over years and over an ambient temperature range from 5deg to 35deg Centigrade can be achieved
even for a 144MHz VCO with temperature compensation and no thermostat, using double-gate MOS-FETs, for example.
What is bad about the BF245A? The small gate-to-channel capacitance of a few pF is important for frequency stability. That's why my simple
60kHz test oscillator drifts by only 1ppm when VCC is varied from 8 to 10V.
It has occurred to me that my reference to the frequency shift with supply voltage is no good way to judge the oscillator modulation by low-frequency flicker noise; rather the frequency shift with Vgs is called for. I have experimentally determined this to be close to
10Hz per 100mV (by inserting a DC voltage source at the bottom end of the source resistor).
The only BF245 datasheets providing noise data are those by Philips and Siemens; and these don't reach below 1MHz. However, the 2N3819 should be very similar to the BF245, and for this the Vishay-Siliconix datasheet does show an input-referred voltage-noise curve ending at
20 nV/Hz^(1/2) for 10Hz (for a Vgsoff=3D-3V device at Id=3D5mA). This extrapolates to 200 nV/Hz^(1/2) at 0.1Hz.
Thus, over a 10s measurement interval, the typical Vgs offset will be of the order 200nV, and the corresponding frequency offset of the order 20=B5Hz, or 3*10^-10.
Unless there is another, more important mechanism!
If you change to a higher frequency JFET and operate it with lower node impedances, you can reduce the JFETs ability to pull the frequency. Also giving up more voltage in the source resistor can help by reducing the variations in gain.
I suspect that the inductor will be as much or more problem than the JFET. If the assembly is not very well shielded, the inductor can pick up noise. If the inductor has a core, the inductance can be changed by local magnetic fields. Any mechanical stress or thermal effects will also change the inductance.
If your just looking at the noise for achedemic reasons and ignoring other effects then 1/f low frequcny noise is the most significant factor if you are looking to average over 1 second or so, this is becuse the low frequcncy noise modulates the amplitude and phase of the signal and so cuases sidebands wich are so close to the fundamental that they are not atenuated by the LC circuit unless you have a Q wich gives you a bandwidth of 1 hz.
fets have the worst 1/f noise compared to bipolar, if you trying to design an optimum circuit then you need to decide what errors are most costly to you. I dont think its worth considering 1/f noise with LC circuits as the L, C wil drift so much anyway.
Im looking at low 1/f noise XCO atm and am looking at using a xtal bridge as a FM slope detector and AFC to reduce 1/f phase noise.
In article , colin wrote: [..use a high frequency JFET.]
How does the 1/f noise modulate the phase significantly if the JFET can't control the frequency significantly? If the JFET is a high frequency one and it is connected to lowish impedance nodes, this would seem to remove its ability to modulate the signal's frequency.
This is a different issue than the JFET simply adding noise. At a frequency of many KHz, the 1/F noise is small for a good quality JFET.
My inductor is not shielded and I had looked into environmental electro-magnetic noise around f0 (CCIR data), but had completely ignored frequencies around 0.1Hz. This is an interesting angle! (I'm in a residential environment ... and then there is the geomagnetic field .=2E.)
The BF245 already is a fairly high frequency device: gfs drops to 70% at
700MHz typ. The tank impedance (50ohm at the tap) of my circuit is below the FET output impedance (1kohm). Shouldn't one increase the output impedance to reduce pulling, then, rather than the other way round? Anyway, the tank impedance (L/C)^(1/2) in relation to the FET output impedance determines the oscillation amplitude; you don't have much freedom with a simple self-limiting circuit like this.
Actually, for my test circuit, the frequency shift with Vgs is 4Hz, not
10Hz, per 100mV (the 1=B5 X7R blocking cap on my voltage source was too small and had introduced a phase shift of its own; I had to add a 100=B5
tantalum). So, over a 10s interval, an expected modulation of the order
of 8=B5Hz, or 1*10^-10, results.
col>
ncy
L,
as
Thanks for confirming modulation of f0 by FET flicker noise as the dominant mechanism (as long as instabilities in L and C can be ignored). But I may have to look into the pickup of low-frequency environmental noise by my inductor in order to get down to 10^-10 ...
Ken Smith wrote:
Maybe I shouldn't speak for Colin, but this is the way I see it: One should think here of "affecting" rather than "controlling" the oscillator phase or frequency. My measurement of frequency shift with superimposed
DC gate voltage just quantifies such a kind of influence. The low-frequency noise from the FET channel will act in precisely the same manner as long as the noise frequency stays within the bandwidth determined by the tank-circuit Q. Whether or not the effect should be called "significant"=20 very much depends on circumstances.
It depends on what about the FET does the pulling. The gate capacitance acts a little like a variactor diode. Keeping the impedance at the gate node low, reduces the pulling effect of that capacitance.
The gm of the FET is effected by the current it is run at. If you use lower node impedances and higher drain current, generally the temperature effects on the phse shift will be less.
You could add the 3rd capacitor and a new bias path to allow you to break the two issues apart.
Beware of all capacitors that are not NPO. If there is any AC voltage on them, they can start controlling the tuning. I'd want to use a 0.01U, a
1U and 100U to make sure that the impedance is very low over a wide band. EMI coming in through the power wires is also a source of FM noise.
[...]
When you finally get it working, you are certain to find another noise source we haven't thought of. It is likely to be something like Barkhausen noise or some effect in the PCB material. This is where science meets the black arts.
Mumetal is the easiest way to solve the problem of magnetic fields. If you make the box from "tin plate", solder the joints and then degauss the assembly, you can get fairly good shielding.
Typically a layer of metal lowers the external field by a factor of 10. 3 layers of Mumetal with about 1 cm between them will reduce external fields by a factor of about 1000. I suggest making the overall box out of iron, putting the oscillator section inside an internal box and then shielding the inductor.
The iron boxes each add thermal mass too. Each layer of metal and air/foam will also help to keep external temperature variations out. A good thermal control design will be needed. Thermal mass is your friend in the short term if you don't mind long warm up times.
1e-10 is OCXO turf. A good LC oscillator (and this isn't really a good oscillator circuit... loaded Q is too low) might be 4 or 5 orders of magnitude worse.
well for a start there will be some non linearities in the circuit so it will have a mixing effect, and the products of mixing low frequcncy 1/f noise will be sidebands very close to the Fo, so even if it doesnt atcualy shift the frequcncy directly it adds an offest to it.
also any noise that cuase changes change in operating point will have an effect on frequcncy if it alters the parasitic capacitances.
also any noise will efectivly apear as a phase error if it is used in highly non linear mode, and a changing phase erroor = change frequcncy.
the 1/f noise much above 1khz isnt going to be the problem as its mathmaticaly implies that it falls with increasing frequency, it is likely the LC will have suficiently high Q to have a bandwidth of 1khz and block this noise anyway.
the point at wich the 1/f noise rises with falling frequency generaly ocurs at a considerably higher frequcncy with fets than bipolar, aparently, if you look at numerous data sheets that actualy specify it anyway, I dont know what exactly actualy makes the diference although I think generaly 1/f noise in semiconductor is to do with defects wich act as charge traps.
you can get good noise performance with fets, indeed if you have a very low chanel resistance wich usualy implies quite a high current to get any gain, as it is this resistance wich contributes to the noise voltage, just as the resistance in the base/emiter contributes to bipolar noise. however i dont think this solves the problem of the frequcny at wich the 1/f noise starts to rise.
also if you use high the high input impedance of the fet to maximise the input voltage then you gain considerable signal to noise ratio, and also maintain a high a Q as posible to filter it out.
one might think that a completly linear design would be best but interstingly there seems to be an advantage in using highly non linear techniques in oscilator design, any phase error in the drive to the tank circuit will have maximum effect if it ocurs during the zero crosing point, conversly if a short pulse is aplied at the peak it apears that any phase error in this pulse has less efect.
dont forget also that although you calculations may show only an extremly small amount of noise may be introduced into the system, if it is within the bandwidth of the resonant circuit it will be multiplied many many times by the positve feedback loop. Therefore there is advantage in having a controled amount of gain.
No, mixing by multiplying makes equal side bands. The amplitude varies but the frequency remains exactly the same. This is why I was suggesting making sure that the amplifier is good to a much higher frequency than needed. A distortion that acts only on the instantanious voltage, always creates equal sidebands.
I stated this happens and that, this again is why I suggested low AC impedance nodes at the FET. This reduces the effect of any variation in capacitance.
No, this is not true. Noise that is identical side to side WRT the carrier does not effect the phase.
Yes, I said as much in an earlier post. This is assuming that the node impedance at the FET is low enough that the capacitance modulation can be ignored.
[...]
No, this is not true. You can run a larger voltage on the inductor to keep the voltage at the gate the same as you lower the impedance.
A very high Q tuned circuit has a high enough impedance that the noise current of the FET starts to matter too.
No, the gate of the FET has a real component to its impedance. If you add the 3rd capacitor, you can split the issues apart. You also don't want the capacitance of the gate to be anything close to the capacitance that is doing the tuning.
This is certainly not true. ALC style oscillators are what you use if you want the most stable frequency. Clipping and distortion of any type allows the noise components near the harmonics of the carrier to be re-introduced as near carrier components. This reduces the performance a great deal.
I flat don't understand the intent of that statement.
You would be correct if the circuit had a flat flat phase and balanced amplitude response about its operating frequcncy but this isnt necessarily so, it depends largly on the feedback topology.
Although I cant say ive gone into the maths of how altering the amplitude/phase of the sidebands affects the phase of the output in any great detail, the modulation gets in there somehow, If you look at the sidebands of a typical good oscilator the close in noise rises at 1/f^3 this is due to 1/f noise and the 1/f^2 response of the resonant circuit.
Amplitude modulation on its own isnt too much of a problem anyway as this can be eliminated with AGC/limiting.
The ratio of parasitic capacitance seen by the tank circuit to capacitance of the tank itself would determine how much this would afect the frequcncy. If you have a high frequcncy oscilator you cant make this very large, despite that the impedance would be quite low.
highly
If it moves the operating point of the circuit then this may have an effect on the delay through the amplifier and hence phase. also non linearities will efectivly make the noise no longer identical side to side of the operating point.
I dont see why you think this is not true, many RF FET datasheets specify noise performance by using 50 ohm mathcing networks wich also step up the voltage, this is how they arive at such spectacular noise figures.
Noise current of good FETs/MOSFETs is small, realy small, ... down to a few fa/rt hz. its proportional to the gate leakage current, this alows for impedances of megaohms before noise curent comes significant compared to noise voltage. althought the 1/f current noise corner is often at a significantly higher frequcncy than the voltage noise corner.
The real part of the impedance is a lot higher than a bipolar (wich i think was the point i was trying to make), especialy at lower frequencies.
Its all swings and roundabouts, you have to wiegh up the cost of doing one thing or another, ie higher signal for better SNR but lower signal if you want improved linearity or beter Q, .. higher capacitance for less efect of parasitics but optimum Q may be acheived with lower capacitance ...
at low frequencies the tuning capacitance becomes high enough for parasitics not to be an issue, at high frequencies you can use RF MOSFETS wich have remarkably low input capcitance or dual gate wich largly avoids the most troublesome feedback capacitance.
point,
The harmonics will be greatly attenuated by the tank circuit before they can be re introduced close to the carrier frequency. Although im not too clear of the exact mechanism where they get introduced this way I would think they get would be attenuated considerably anyway and would be much less than noise close to the Fo and especialy compared to the
1/f noise wich would still dominate, any significant reduction in 1/f noise will probably offest the slight increase in noise harmonics.
It also depends very heavily on the type of harmonic distortion that occurs ie odd or even harmonic. even harmonic typical in the type of single transistor design being the worst in some circuits, and odd harmonic, such as with balanced clipping having much less effect in some circuits than other types.
When I was looking up ways of reducing phase noise I came accross some work on this, look up "Oscillator Phase Noise Reduction Using Nonlinear Design Techniques" wich i was quite surprised by, and also by how involved the issue of close in phase noise is in general, theres lots more than what i could realisticaly go into witout some specific objective.
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by
At the fequency of oscillation the gain of the total loop will be slightly greater than 1 to sustain the oscillation frequcncy, any noise that gets introduced that is close enough to the center frequcncy so that it is still within the response of gain >1 will be amplified significantly.
After all the oscilation frequency is in fact just the noise selectivly amplified many many times by positive feedback, therfore what im saying is that the close in noise in the output is much much greater than simply the voltage noise at the input.
Thus keeping the gain as low as posible will ensure the bandwidth with gain
Colin, what is the reasoning that makes you conclude that white noise from within the bandwidth determined by the tank-circuit Q is no factor
for a simple self-limitimg FET oscillator like mine? How large could that contribution to the frequency noise observed on a 10s scale be? I have no clear idea how to estimate this. (The input-referred white noise level of the 2N3819 is around 3 nV/Hz^(1/2), my loop gain is only moderately larger than one, f0 is near 60kHz, the unloaded Q is around
The reasoning is that for a bandwidth of .1-10 hz the 1/f noise is several orders of magnitude larger than the white noise, for a good device 100 times larger wich from data sheets amounts to somthing in the order of ~0.1uv pk to pk for bipolar and ~1uv pk to pk for FET, some device are well in exces of 1000 times the white noise, some even more, most spec sheets for low noise low freq devices dont even specify noise below 100hz, and its hard to find specs at all for most devices for this f range, probably becuase it looks embarising. some RF devices dont mention noise performance below
10mhz.
Even if the mechanism for modulating this noise onto the carrier is low it is still quite likely to be high enough to allow it to become dominant
Although its not clear how much of this is due to modulating the parasitic elements and how much is due to actualy mixing unless you examine a particular circuit in detail, ive worked with xco wich are much higher frequency and so you are limited to tens of pf, maybe your circuit baheves diferently but with a Q of 20 compare to a Q of 20,000 for a crystal ...
Also as I mentioned the noise profile of the output its clearly dominated by
1/f noise very close into the carrrier as the noise rises at 1/f^3 where f is the distance from the carrier. further out from the casrrier it returns to 1/f^2 wich is white noise atenuated by the Q of the tank.
Also although your loop gain is marginaly larger than one this circuit has positive feedback, therefore the actual closed loop gain is high, if you try to work it out you will find it comes out as infinite, but it is limited as when the output increases the gain falls.
If you get 2 identical oscilators in a PLL with the loop time constant of less than 1 second you can see the phase noise from the output of the phase detector on a scope, ... it jumps around a lot, when I first encountered this I thought it was faulty components soldering or whatever etc, and although vigourously cleaning of the flux helped sometimes even after rebuilding them carfeuly with new components it was still there, I threw away many a good oscillators in disgust before i cuaght on to this.
There are some methods and programs wich estimate oscillator noise but these are rather limited frtom what I can gather as it is an extremly complex issue involving so many factors, especialy so for close in noise.
Also as has been mentioned before drift due to temperature etc will more than dominate noise anyway.
If you realy want a 60khz oscillator that remains totaly stable over a 10s interval I sugest you consider a crystal oscilator and divide it down.
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