Hafnium to replace silicon dioxide as isolation layer in new Intel processors?

Typo? Hafnium is a METAL...

Tim

-- Deep Fryer: a very philosophical monk. Website:

That was my first reaction. Possibly the new gate insulation is hafnium oxide or nitride, or some other hafnium compound that has a high dielectric constant, high insulation resistance and compatibility with the silicon lattice spacing and other process compatibility. I think we are getting the daily news version of the details.

I found an article that goes into more detail. It seems they are talking about hafnium oxide.

On a sunny day (Sat, 27 Jan 2007 23:29:07 -0600) it happened "Tim Williams" wrote in :

Hey, cleaver, did not even occur to me, I was still in 'dioxide' wondering if that was right..... Anyways now everybody is screaming they will use it, Intel in 2007, and IBM says

Looks like it is a big deal.

if

says

nothing

Yeah. I saw this yesterday on one of the newspapers on my Google "homepage". A quick Google for hafnium +transistor gave lots of articles about high-k Hafnium silicate/nitride/silicon oxynitride etc. insulator films, and _one_ mention that something other than polysilicon (Intel in particular says a new, "secret" alloy) is needed to make the electrodes on the Hafnium-whatever films.

Maybe not such a big deal until _after_ somebody runs a burnin on a few wafers.

Mark L. Fergerson

says

nothing

Classical CMOS scaling has more or less completely broken down, because it's run into quantum-mechanical and electromagnetic limits.

In order to turn a FET on and off, you need a certain electric field throughout the channel region to sweep the carriers out. Historically we've maintained that by thinning the gate dielectric as VDD decreases and dimensions shrink. That doesn't work any more, because as you make the dielectric very thin, you start to get electrons tunnelling between gate and channel, which leads to large leakage currents. If you back off on the dielectric thickness scaling, you don't have the E field you need to turn the FET all the way off, and so you wind up with drain-source leakage. Both of those are serious limits today, and are getting worse.

People have been trying various things to fix this, including wrapping the gate round 3 sides of the channel instead of one, which is the basic idea of the FinFET, and using high-K gate dielectrics instead of SiO2. For a given thickness, high-K tends to make the tunnelling problem worse, because it effectively reduces the height of the tunnel barrier. However, it also allows you to use much thicker dielectrics, and since the tunnel current goes down exponentially as the barrier thickness goes up, you win by going to high-K.

People have been working on this problem for years, and everybody has known for a long time that high-K was going to be needed in the next generation or two. It won't save CMOS scaling, but it's definitely useful.

Cheers,

Phil Hobbs

High-K gate dielectrics

Speaking of pinheads,

I'm surprised that Gordo would make such an inane statement...

Gordon Moore, co-founder of Intel, said: "This (development) marks the biggest change in transistor technology since the late 1960s."

John