Frequncy generator

oops

I would say not.

The 40Hz comparison frequency is too low. That's going to force you to use a very low loop bandwidth, which will make it slow to lock.

You'd probably need to convert the mixer inputs to sine waves first; and it'll produce sum and difference products, so you'd need a good low pass filter to remove the 10.4-13 MHz sum product whilst passing the .4-4 MHz difference. Finally, you'd need to square-up the sine waves again before feeding them to the dividers.

If the aim is to produce low frequencies with high resolution, how about a DDS?

If you want a PLL with small steps, consider Fractional-N.

That is a concern. Once locked the loop filter can be slow, and I had thought to use a lock detect circuit to change the current of the detector for speeding up lock time.

Had a D FF in mind for that part, only the difference out.

Had a brief look, still reading.

Will research. Thanks.

Only if you can tolerate immense amounts of phase noise.

This sort of thing looks ideal for a cheap DDS chip. I'd maybe double the clock first, to 20 MHz, to not run too close to Nyquist.

John