Freq. Independent Phase Shifter

ET

Time to fire up your spreadsheet and give it a try.

The amplitude error on the 90 degree version is about 0.36% with a max phase error of 0.03 degrees assuming ideal parts

Rpot=3D1000 RtoWiper=3D1805 Rneg=3D-667

eFET

.

Ohh neat, I was going to try 2k as a guess.

Ahh, you did all the work for us.

I've never built an AGC circuit Jan, there must be some amplitude error as the input changes.

OK that's not quite true, I've made a rectifier, integrator, minus reference level driving FET as varible feed back resistor... MooseFET's circuit is much easier.

George H.

PS Seems like DDS beats it all.

oseFET

de.

These are the numbers for the 0..90 degree case For the 0..100, case, I will let you do the figuring The 120 degree case requires quite a low Rneg I suggest avoiding that case if you can.

The phase changes with the input amplitude in a way that varies with the frequency so an AGC is not a good thing to put into a frequency independent phase shifter

If you don't mind doing a little coding, you can do it with one of those Analog Devices ADUC70xx devices on the development PCB.

I have also done in it on the Silabs micros.

If you make the DAC update rate 42949.67296 Hz, the math comes out easy to get frequencies as nice round numbers. Unfortunately it means that the phase values are a little ugly but not too bad.

119.3046471111111111 looks bad until you multiply it by 2^24

On a sunny day (Wed, 12 May 2010 18:41:57 -0700 (PDT)) it happened MooseFET wrote in :

Have not use spreadsheet for at least a month.....

That is acutally very good.

Better remember that :-)

Thank you for the correction, I will think about this until I figure it out.. hehe

On a sunny day (Wed, 12 May 2010 20:51:37 -0700 (PDT)) it happened George Herold wrote in :

Nice for such small ranges, you can stil have constant amplidtude with AGC over a factir 100 and more signal level change. Take any old AM radio.

So have I, for audio.

Tue, but Istill have to write down the math one day.

I have seen J.L. posting about programming DDS here, I like just a simple pot to change frequency, and indeed maybe phase, programming a DDS seems much more complicated, and then how do you control it?

--- What does direct digital synthesis have to do with generating two sine waves 120 degrees apart over a range of frequencies?

Hmm, Can't you just have a simple offset from two look up tables. Run them off the same clock and change the clock rate to change frequency. Some one already posted that I thought?

George H.

Here's a diagram helpfully supplied by a previous poster:

"FIN>---[COUNT]-+-[LUT 0°]---[DAC 0°]--->OUT 0° | | +-[LUT n°]---[DAC n°]--->OUT n°

How it works is that for any given output from the counter, the LUTs will have outputs which, after being run through the DACs, will differ from each other by the difference in voltage/current caused by the difference in phase between them, that difference being programmed into the LUTs."

See, the sine waves are coded in lookup tables and are Directly Digitally Synthesized via the Digital to Analog Converters. John Larkin suggested turning it into a State Machine that would allow it to select portions of the lookup table for coarse frequencies across a wide range with high resolution while using a relatively low clock rate (and commensurately cheaper parts).

--Winston

One can stick an N-bit binary adder (N being the same as the counter width) to add a phase shift to one path, and use the same lookup table contents, or share a single table. That way you don't have to reload the table to change the phase shift. If you stuff M into the adder, the phase shift is 360 * M/N degrees.

That works for both the binary counter and for the DDS accumulator versions.

John

Once you have the DDS logic set up, it's really easy to stick an adder into one of the address paths and add a 0 to 359.999... degree variable phase shift. A small FPGA and a couple of DACs can make a nice generator with huge frequency range/resolution and pretty impressive amplitude and phase control.

John

--
Indeed. 

My quarrel was with "DDS" being used as something other than the
mechanism used to generate the variable clock from a fixed frequency
source.

Not exactly. If you address the sine lookup table with a fixed-frequency-clocked phase accumulator, instead of a counter, you can tune the sine frequency to as fine a resolution as you want, just by using more bits in the accumulator. If you put a decent anti-aliasing lowpass filter after the DAC, you can make beautiful sine waves at frequencies approaching Fclk/2, namely the Nyquist frequency. As a practical matter, Fclk/3 or Fclk/4 is easy.

This uses an FPGA clocked at 128 MHz, a 32-bit phase accumulator, a

4096 point sine lookup table, and a 14 bit DAC per channel. It makes sines from 0 to 32 MHz with 0.015 Hz frequency resolution. It's a textbook DDS design, but with phase-rotation adders in the lookup table address paths and multipliers for amplitude. There are also adders into the accumulator inputs to allow FM and chirps and such.

Here's the board:

ftp://jjlarkin.lmi.net/DSC01786.JPG

What's cool is that you can put negative numbers into a phase accumulator and walk the sine table backwards, generating negative frequencies. That's handy for making, say, quadrature microstepper drives and running the motor clockwise or CCW.

John

Thanks John that makes it easier.

George H.

Ahh, I wasn't quite sure what your 'quarrel' was. Would you have been happier if I'd just said digital techniques?

George H.

Oops, the phase shift should be 360 * M / (2^N) of course.

As the DAC output frequency approaches Nyquist, the DAC waveform looks perfectly awful, all steppy and squirmy and random-noisy looking. It's hard to believe that something's not broken. After the lowpass filter, it's a beautiful steady sine wave.

John

(...)

(...)

So the Phase Accumulator itself is a state machine which creates a binary version of the next point to be output predicated on the previous point and the frequency control word.

It is starting to soak in. Thanks!

--Winston

I guess.

Imagine a 32-bit clockable binary register, just 32 D-type flipflops. Call the value in the register R. Every clock, add a 32-bit value F to it. so

At every clock

R = R + F

F is our 32-bit frequency set register.

If R=1, it will take 2^32 clocks for R to make a full cycle back to where it started. If R=2, it will cycle around in 2^31 clocks.

Take the 12 most significant bits of the R register and use them to address a sinewave lookup table, and use the result to load a DAC at the same clock rate.

What's cool is that you can put all sorts of values into F, and the frequency of the DAC is proportional to the value F. For small values of F, it will take many clocks before you bump the upper 12 bits and advance one location in the lookup table. As F gets bigger, you'll start hopping around the table in bigger jumps, skipping some entries. But if you lowpass filter the DAC output, you always get a sine wave. The frequency-set resolution is Fclk/2^32, which is pretty fine. If you use a 64-bit register, resolution is Fclk/2^64.

It's really very simple, an easy to build in an FPGA.

John

Nice. For sine wave, DDS is a good idea. But when you generate a square wave with your device with e.g. 31.7 MHz, what is your maximum cycle-to-cycle jitter?

BTW: Where can I buy your devices and do you have a price list on your webpage?

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

*Much clearer!* Thanks for the explanation.

--Winston