Flexible Instruction Set Encoding.

Also I am not sure what you mean with code size ?

If you mean "operand size".

Then AMD probably did not include something like that because the manual clearly says the rex prefix must be used to specify a 64 bit operand size ! ;)

Except for instructions that modify the RSP.

No idea yet what RSP is... 64 bit stack pointer ?

Bye, Skybuck.

Reply to
Skybuck Flying
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Where in the manuals can I read about this ?

(So far I am reading the intel manuals ;))

Maybe I should give the AMD manuals a try ! ;)

Bye, Skybuck.

Reply to
Skybuck Flying

This is called the instruction prefix which is added before each instruction.

This means either two things:

  1. Write two code paths. probably because he does no reading, no research.

This remains to be seen.

Your lack of accuracy will prevent you from ever turning up any prove what so ever that my invention was already invented ;)

Bye, Skybuck.

Reply to
Skybuck Flying

You really do have a problem communicating with people, don't you? You've managed to insult and alienate everyone who has tried to give you help in developing your programming skills and ideas. These are people with far more experience than you of *real* programming, not just obsessing about meaningless details. They have given polite and thoughtful answers, but you respond with all the social skills of a badly raised ten year old. Tagging an "LOL" on afterwards does not make it any better - it just makes you look even more childish. Come back to us once your voice breaks.

Reply to
David Brown

Mary Ann had brains, too. Think about it. Who only had two neurons left?

--
Service to my country? Been there, Done that, and I\'ve got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida
Reply to
Michael A. Terrell

That depends a lot on the compiler, the processor and the routine around it. The simpler the code, the more the overhead will show. If you look at a longish routine, you will see that the overhead is quite small compared to the other code.

The call method involves a "call" and a "return". The jump method needs two jumps. A very smart compiler can pick the faster way.

Reply to
MooseFET

I had typed in some interesting stuff pointing out some cute tricks in the design of CPUs and software that you may have found useful. I then saw the insult. I don't see any point in bothering.

Reply to
MooseFET

With a bit of trickery, you can do the same with C using include files. You can change the "#define"ed constants and include the same code section over and over again.

This lets you have the same code file create the different sized and swapped endian versions of routines.

Reply to
MooseFET

I need some clearifications concerning this L thing you mentioned:

" 4.2.1 Code Segment Descriptor in 64-bit Mode

Code segments continue to exist in 64-bit mode even though, for address calculations, the segment base is treated as zero. Some code-segment (CS) descriptor content (the base address and limit fields) is ignored; the remaining fields function normally (except for the readable bit in the type field).

Code segment descriptors and selectors are needed in IA-32e mode to establish the processor's operating mode and execution privilege-level. The usage is as follows:

. IA-32e mode uses a previously unused bit in the CS descriptor. Bit 53 is defined as the

64-bit (L) flag and is used to select between 64-bit mode and compatibility mode when IA-32e mode is active (IA32_EFER.LMA = 1). See Figure 4-2.

- If CS.L = 0 and IA-32e mode is active, the processor is running in compatibility mode. In this case, CS.D selects the default size for data and addresses. If CS.D = 0, the default data and address size is 16 bits. If CS.D = 1, the default data and address size is

32 bits.

- If CS.L = 1 and IA-32e mode is active, the only valid setting is CS.D = 0. This setting indicates a default operand size of 32 bits and a default address size of 64 bits. The CS.L = 1 and CS.D = 1 bit combination is reserved for future use and a #GP fault will be generated on an attempt to use a code segment with these bits set in IA-32e mode.

. In IA-32e mode, the CS descriptor's DPL is used for execution privilege checks (as in legacy 32-bit mode). "

" If CS.L = 1 and IA-32e mode is active, the only valid setting is CS.D = 0. This setting indicates a default operand size of 32 bits and a default address size of 64 bits. The "

As you can see from the text above, the default operand size remains 32 bits.

There is no easy way to convert exisiting code from 32 operand size to 64 operand size or vice versa.

Maybe they could use:

" CS.L = 1 and CS.D = 1 bit combination is reserved for future use "

To implement it.

Possibly and interesting discovery/idea that's why I renamed the topic so this text is easy findable and people hopefully notice it in this messy thread ! ;) :)

Bye, Skybuck.

Reply to
Skybuck Flying

EXACTLY.

The whole idea is too minimize all other overhead.

To get a very good idea how much this single switch adds in overhead.

If this single switch is done everytime a calculations must be performed then ofcourse it's really important to test how much this single switch adds in overhead !

Let's face it, this test is a optimal test there is only one branch maybe two that get called, so branch prediction should be 100% optimal. The branch taken is always the same.

So even during this optimal condition test the OVERHEAD IS HUGE.

That means during a real program the overhead might even BE WORSE.

Not that much difference between a jump and call.

Bye, Skybuck.

Reply to
Skybuck Flying

Blablablablablablablabla LOL.

Others have insulted me as well, and they not joking it seems.

Some simply assume there 16/32 bit knowledge simply translates to the 64 bit case.

I have discovered this is not the case.

Not all features are present in the 64 bit design of AMD.

Especially the segment descriptor mode switch for default operand size 64 bit is missing !

AMD could implement it by using the reserved bits (CS.L=1 and CS.D=1) for future use, me thinks !

And there ya have it folks !

Skybuck telling you people how to extended your limited processors !

A nice symbioses between old farts and young talent like me ! LOL.

Bye, Skybuck.

Reply to
Skybuck Flying

Good because you are the one with the thick skull if I am not mistaken ! ;)

Bye, Skybuck >D

Reply to
Skybuck Flying

Arrogance and ignorance usually go hand in hand :)

Reply to
SpooK

Usually after you treated them with insults, insinuations and stupid remarks. It was you who most of the time behaved like an idiotic badly raised teenager.

Your "blablabla LOL" is another example. You obviously have never learned to get around with people. People are much more likely to actually help you (and you need a lot of help, even if you think you know everything already - your utterances show you are extremely inexperienced) if you treat them respectfully. They are much more likely to treat you respectfully as well.

--
Rudy Velthuis        http://rvelthuis.de

"It is much more comfortable to be mad and know it, than to be 
 sane and have one's doubts." -- G. B. Burgin
Reply to
Rudy Velthuis

Typical, now you people must admit defeat you get personal and start trash talking LOL.

That's the sound of victory ! =D

HAHAHAHAHAHAHA

Bye, Skybuck.

Reply to
Skybuck Flying

We have enough people around here who blow smoke and declare some sort of "victory" with blatant disregard to reality and fact. Pity that you should start that at such a (self declared) young age. Soon enough, you will find yourself turning in to a Straw Man incarnate.

Good luck with how far your myopic point of view gets you in this world :)

Reply to
SpooK

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