Faster buffer than NL37WZ16US anywhere?

Folks,

The NL37WZ16US can muscle a 50ohm load around in under a nanosecond when paralleling all three sections in it. This is great. But of course once you have a Porsche you then want a Ferrari. Is there by now something even faster, like 100-200psec?

Must be push-pull output which rules out MMICs, supply is 3.3V, output Rdson values should be as low as possible or at least somewhat predictable, $2-3 in qties is ok, quiescent current draw should be in the low single-digit mA. It doesn't have to be a logic series chip.

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Regards, Joerg 

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Reply to
Joerg
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How much swing do you need?

MC10EP89? That's push-pull if you pull down hard enough.

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John Larkin         Highland Technology, Inc 

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John Larkin

1V would suffice, even 500mV would be tolerable if fast enough. So we could also live with devices for lower voltage operation. If absolutely necessary.

That would blow our power budget, plus I need to be totally matched to line impedance while pulled up and pulled down.

I could design all this in discretes using RF transistors but that would not fit into the tight real estate constraints for this case.

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Regards, Joerg 

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Joerg

TDR step source?

Can I sell you my deconvolution algorithm?

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John Larkin         Highland Technology, Inc 

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John Larkin

Den fredag den 23. maj 2014 19.30.05 UTC+2 skrev Joerg:

I haven't tried it, but something like this?

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-Lasse

Reply to
Lasse Langwadt Christensen

Yes, something like that. I need to push more lower spectrum energy into the load versus just a small pulse.

Not to me but maybe some day to a client. Deconvolving after a less than ideal spike hasn't been a problem but the thing is that it lacks spectral energy to detect gradual impedance changes over time. That puts a damper on the resulting SNR in such situations.

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Regards, Joerg 

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Joerg

Clock buffers go in the right direction. This one appears to be roughly on par with the NL37WZ16US. Maybe a smidgen faster at 5V supply but that would be hard to provide in this case. No space for a little switcher or charge pump.

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Regards, Joerg 

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Reply to
Joerg

The WZ16 rise is closer to 500 ps

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The OnSemi gigacomm stuff is really fast, but outside your power and cost budgets.

NB7V52MMNG is interesting.

You could drive a couple of SRDs from a cmos gate. HP made one pulse generator pretty much like that, screaming edges. MA44769-287 maybe.

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John Larkin         Highland Technology, Inc 

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John Larkin

Ok, let's say that is 750psec :-)

That could melt the polar ice caps and then the warmingists would picket our street.

I could also whip that up with RF transistors, stripline baluns and other parts. Unfortunately there just isn't any space except for one SO-8 or similar package.

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Regards, Joerg 

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Reply to
Joerg

maybe this?

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-Lasse

Reply to
Lasse Langwadt Christensen

The NL37 is tiny. Then you'd need a couple of SOT23 SRDs. And some passives. Possibly as little as a single capacitor, if you got lucky.

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John Larkin         Highland Technology, Inc 

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John Larkin

Am 23.05.2014 21:45, schrieb Joerg:

ADCMP580 family? single digit mA are hard if you have a current switch,

50 Ohms doubly terminated and half a volt RF.

if you would want more level: <

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Reply to
Gerhard Hoffmann

We've used the ADN2871 as a phemt gate driver. We had to really persuade Analog Devices that we were worthy of using that chip, especially as we weren't driving lasers with it. There is some AGC/ALC sort of stuff inside that you have to defeat, and DC coupling is possible but not obvious.

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John Larkin         Highland Technology, Inc 

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John Larkin

Thanks, that one could be a winner. A bit high in power consumption and wimpy in drive capabilities but one could parallel outputs I assume.

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Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

Technically that could work, Gerhard. But 14 bucks is a bit too steep and it looks like we'd have to design in a nuclear power station to feed it. Also non-stock except for Rochester.

I just had a very disappointing support case. It seems they outsource some of this and they literally dropped the ball on me. Well, their competition didn't, so ...

That's something I never experienced with AD, they always had excellent support.

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http://www.analogconsultants.com/
Reply to
Joerg

If 250ps typical would be good enough, then I have mentioned on here a couple of times that you can do that with LVC series CMOS.

Here is a video of a 74LVC04AD that I put on a board, in this case the chip was an old one from Philips, now NXP. Unfortunately eevblog tested it with a lower freqency than I had intended, and so the on-board decoupling did not have enough capacitance at the lower frequency and there is quite a bit of ringing on the supply. The low-portion of the waveform looks much nicer because the supply ringing has less effect when the nmos fets are pulling the output down to ground. I think he also removed my ac-coupling and back termination on the output, but you can see that the edge itself has about 250ps rise time, even using whatever BNC adapters he used.

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Chris

Reply to
Chris Jones

Unfortunately Youtube has become totally unreliable out here and this one won't start either. It's hit or miss. Maybe they don't pay enough to ISPs for data throughput.

But if you got 250psec into a regular coax then I ought to try it. So far we have a discrete transistor solution now that does around 100psec but it is larger in real estate (unless we go to 01005 parts and stuff).

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Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

Yes, with good layout and a 14 pin SOIC package you can get about 250ps with a back-termination resistor feeding into a semi-rigid coax (and definitely better than 300ps), at least with the batch of Philips

74LVC04AD chips in my cupboard. I once tested it myself when I had access to a very fast scope and I think that is quite likely a limitation of the chip or package, so I wouldn't hope for much better than 250ps from that device. I did crank the supply up to near the absolute max spec. to get more output but I think that has only a weak influence on the rise and fall times.

I used three gates in a row to buffer and square up the waveform then fed it to three more gates connected in parallel to provide low output impedance. If I wanted a really nice waveform then I would suggest putting the pre-buffers into a separate package because you can see a little tiny pre-pulse that might be coupling from one of the earlier stages directly to the output, or ground bounce of the on-chip ground rail.

I suspect that the 1nH or so in each of the bond wires is likely to prevent any chip with bond wires from doing a lot better. Putting several output pins in parallel at least reduces the effective inductance somewhat, but doesn't help with the power and ground pins. You could try setting some spare output pins high and low, and connecting those outputs high and low externally (or all through capacitors to the ground plane) also, to use them as extra supply and ground pins. Maybe some of those chip scale BGA packages might do slightly better due to the lack of bond wires. Of course if you are using a back termination resistor before the coax then the chip sees 100 Ohms instead of 50, and if inductance happens to be the limitation then the L/R time constant due to bond wires will be better with double the R.

What we really want is some logic gates made on a 0.18um or finer process, and using core devices as the output transistors so that the inherent rise/fall time limitations of the transistors will be much better than LVC etc. I would look for CMOS chips with an absolute max supply voltage of about 2.2V or less, as promising candidates.

Chris

Reply to
Chris Jones

Thanks, Chris, that is very good information. I am surprised that an SO-8 package can do this. NXP and TI also make the 74LVC04 in DQFN, VQFN and DHVQFN. Those should perform even better.

My dream would be a tiny chunk off of a Lamborghini-class FPGA but without the need to program it. Just glue logic on that process.

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Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

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