Fast Pulse Generator

I recently acquired (with a 7904) a 7S12, but haven't used it yet. Does that also have mercury batteries?

CH

Am 29.05.20 um 08:43 schrieb Tom Gardner:

That's what you can expect:

Scope has abt. 150 ps risetime, 2.4 GHz BW

cheers, Gerhard

I've seen a faster risetime (~270ps), but it was a borrowed scope so I can't repeat the measurement.

The possible difference is that I used three 74lvc to reduce the current each supplied, and the 143ohm series resistors were based on a guesstimated 7ohm (or thereabouts) output driver resistance.

That was all more than sufficient for my purposes.

I use all three sections of an NL37WZ16 in parallel. Only needs one resistor. The downside is the dreadful US8 package.

No, it uses the S-series heads.

I have a ton of this stuff if anybody wants any, 5-series and 7-series sampling things.

So, 3* the di/dt in slightly shorter leads. I haven't got a scope that could show me the effect of those differences.

What gets ugly is powering it from, say, 5 volts (or even 7!) but driving it from an FPGA at 3.3 or less. It gets really hot.

This is strange:

The ringing looks real--some sort of charge pump effect perhaps?

Cheers

Phil Hobbs

You might conceivably have electromigration worries if I_Q gets too large. 1E6 A/cm**2 is the usually-quoted limit for top-level copper metal.

Cheers

Phil Hobbs

Nice pictures. Thanks Gerhard.

Cheers, James Arthur

Is that principally a static phenomenon (5V into 50ohms) or a frequency dependent dynamic phenomenon (capacitance and/or both transistors on simultaneously during switching)?

Need more info to understand the source of that.

It's static shoot-through, with front-end pfets and nfets on simultaneously when the logic input is 3.3. The input swing has to stay within about a volt of either rail.

Level-shifting a 3.3 volt swing positive some can help.

An LVDS receiver can be a good level shifter, but that adds a couple ns.

The only surprise to me is the implication that there is a distinct front end / back end, and that the front end has more shoot through.

But I haven't looked at the internals of such gates recently.

All cmos stages have static shoot-thru, but the input stage voltage gain is high, so it's unlikely that the later stages will be railed.

With Vcc=5 or 6, and logic in=3.3, the outputs rail nicely, but the chip gets hot. That's OK to make low duty cycle positive pulses.

In the NL37WZ16 circuit, you can have all three front-ends getting hot together.

err, not railed.

OK; now I understand.

I was presuming the input was from 0 to Vcc, and that also explains your "level shifting" point.

Lucky my limited interest has been a clean fast transition, with delay being irrelevant. Hence I've usually had a single buffer gate driving my three parallel gates, and that was a reasonable 0-Vcc output.

I've also played around with injecting noise (from a diode) into a non-schmitt trigger input, just so I could look at the output spectrum. Fun, not serious, of course.

Terrorist! I spend my life battling jitter, and you do it on purpose!

Actually, one possible option to our new delay generator could be calibrated jitter.

Thought that might tweak your tail :)

General principle: if you know the conditions and can predict how to optimise, then do that. If you can't predict the conditions and can't optimise, then randomise.

That works with electronics, software, networks.

Unfortunately it is also being applied to politics, by people who can't or don't understand the conditions.

Merely for testing, or for more than that?