emitter follower gain

What, you think I'm not interested? That I already have such an exciting life?

Actually not, if you choose the Ic current in the first place to get a nice low e_n, but then discover r_bb' is the big problem. Each of n paralleled transistors is operated at Ic' = Ic / n, there's no increase in the base current, only a decrease in r_bb'.

I mean, yes of course, base current can be a problem, but the paralleling trick doesn't exacerbate it.

What, not tired of electronics yet?

I sure hope I don't get tired of electronics. It's the only thing that I'm reasonably good at.

I thought you were good at making pies?

And bread pudding. But electronics pays better.

His pies are evidently rather painful.

Would bootstrapping the jfet input capacitance help in this case?

Wow, this sounds interesting. I tried some medium-power BJTs for a low-e_n application some years back, exactly hoping to find a low Rbb', preferably simultaneously with a high hFE. A forget the exact types, they were Zetex, too. It wasn't very successful, however.

Regards, Mikko

Usually, that kind of ohmic emitter character is intentional, as a resistive emitter metallization is effective at preventing thermal runaway (second breakdown). This 140V/5A transistor has a safe operating area that limits to 10V at 100 mA. By comparison, TIP31C (100V/3A) has a safe operating area that limits to 80V at 100 mA. I think that means the emitter degeneration resistance was minimized for the ZX... part.

I also have played that game with 10 pairs of ADA4898-2. That may have advantages wrt pssr, drift and temp. dependence. The improvement in en was testbook-like < 220 pV/sqrtHz from

Looks like good fun!

Nice story, Mikko. You would enjoy reading our man-year of experiments and ch 8 writeup, right down your alley.

You can use a jfet as a follower, which automagically bootstraps Cgs, and then you can bootstrap the drain to reduce Cdg. So you can eliminate most of the input capacitance, but get no voltage gain. So, follow the fet with a low-noise bipolar opamp or, better yet, a transformer and more fets, and take care of any DC requirements off to the side.

We're getting into low-noise-no-free-lunch territory.

I wanted the emitter follower in question precisely to bootstrap a jfet drain.

Yup, been there.

A major residual noise source in JFET bootstrapped-bootstraps is the drain bootstrap's noise coupled back via C_DG.

The noise of the current booster (series feedback/Sziklai/PNP wraparound, whatchamacallit) is inside the loop controlled by the JFET(s), so its noise basically goes away. The drain bootstrap isn't in the loop, so its noise doesn't. It doesn't always matter that much, especially if whatever you're bootstrapping has a gross amount of capacitance, so that the FET noise dominates via the omega C_in * e_N mechanism, but it often does at lower capacitance.

I've played with putting the drain bootstrap inside the loop, but it hurts the bandwidth, so the parallelled BJT method is better.

Cheers

Phil Hobbs

Just received the AoE 3rd ed, the story seems to be there, interesting. The ZTX951 hFE is not that wonderful, however, indicating that Tn is not so great - and that's what I'd need with my typically cold generators. The two discontinued classics look better, but they are ..er.. discontinued.

Anyway, I forgot what made me abandon the low Rbb' quest: the fact that there is always cryostat wiring, which must be resistive due to Wiedemann-Franz, and which plays a more significant role that the Rbb'. Cold SiGe transistors are amazing, however. We have a batch of NESG3031's whose hFE peaks at 27000 at 20K. Those can provide gain before the Johnson noise due to wiring adds.

The book looks like a very interesting read, packed with Phil's clever tricks. And those selection tables are truly valuable.

Regards, Mikko

Hi, Mikko,

Welcome back!

I supplied only a minute fraction of the tricks, and they're nicely acknowledged. I agree about the graphs and tables. There's a _lot_ of information there, and it seems to be pretty up to date, which is amazing considering how long Win and Paul have been working on it. (They must have felt like Sisyphus sometimes.)

Cheers

Phil Hobbs

Whoa, the datasheet and has a plot showing 300 near 10mA, rising a bit at low currents. You're saying 27,000?

At 20K. The data-sheets documents the behaviour at room temperature, 298K, or 25C.

With silicon transistors, the current gain usually went up with temperature , rather than down, but Phil will probably be able to explain why SiGe part s might be different.

Bob Widlar at National Semiconductor worked out a way of making super-beta silicon transistors in 1969, and the LM308 depended on their magical proper ties. IIRR the current gain was still only about 3000 and the collector bas e-breakdown voltage was extremely low.