EMC guidelines...true or false?

Provide an email address that ACCEPTS .zip files and I'll send you a copy of the results of using a PCB Layout Tool I created. The Tool QUANTIFIES the effects of noise from IC's across the plane to verify component placement and effectiveness of any planar cuts. ...I got tired of 'shooting from the hip' and saying things like, That looks about right, or that should be enough cut. More importantly, a client wanted the PCB layout right the FIRST time! Thus, a tool to that actually generates REAL numbers.

Hi Robert,

RobertMacy wrote: []

oups! my bad. Indeed the 5cm rule is kind of useless for the L/S bands. I'd say a factor 5 would be needed, but then again the coupling capacitance between the planes may serve well the purpose, but what is sufficiently good? I'm not sure if it's realistic to stich every cm.

We do not have AC mains, we have an unregulated bus at ~50V DC. The application is basically a BLDC motor driver (three actually). Yet there are enough interfaces and complexity to turn the system into an interesting fella EMC wise.

Correct. And considering that EMC tests are performed after all concrete has been poured, the cost to scrap it off because of an EMC NC can be painful.

Likely we are allowed a minimum of ~4 mils (0.1 mm) for quality assurance requirements. If I understand well the 7 dB gain would be due to a better coupling between the ground planes, hence an overall better shielding.

Yes indeed. The metal box has to be conceived with EMC aspects as well, but the design should not rely on it alone. As I said in another post in this thread, an RE issue may easily turn into a CE one if no countermeasures have been taken to limit the emission.

the point is not to transmit *extra* energy, since information is nothing more than energy variation. But it's true that often we distribute clock signals through backplanes and other boards in LVPECL while it would be wiser to extract the clock through the data (like in DataStrobe encoding).

We finally hit a Radiated Emission Non Compliance on the 12th harmonic of our 32MHz clock, hitting one forbidden notch. Truth is that we probably do not need that harmonic and an RF bead may have cleared up the issue.

Yet the high harmonic content does not only act on corners of the signal shape, but also slope. An improper slope would cause extra jitter in the receiver's clock tree and adding temperature and voltage variations we suddenly risk to induce more problems than solve. Yet I do agree that we do not necessarily need to go as high as the 11th harmonic.

As for any risk, there are always two aspects to consider:

1. avoid the risk as much as possible (where is the limit?).
2. take the necessary precautions to overcome the consequences.

dissipation through what?

Take a look at EVERY 2.5GHz App Note's PCB layout. I know it's an overkill for you, bbut they do it, because their energy is AT 2.5GHz. But it's very educational to observe what hey found they had to do.

When I say 'AC mains' and audio; I was referring to the type of thinking associated with that conept of a single start GND with a rod in the ground and, well you know concepts of audio 'grounding'. It's just that when you get into the 100MHz+ bands it'snot the same.

If EMC ocnsiderations are instilled in the minds of the original designers, at least the basic principles; they make decent design tradeoff decisions to head off MANY of those potential problems, before they rear their ugly head, when it's cheap to pre-solve them.

THAT's MY POINT!! design EARLY! Waiting makes the fixes usually timid AND costly, plus there is an unknown delay in development [that can be really costly to cash flow] AND worst of all there is usually such little margin that when you go to version 2; you have the whole battle all over again. [After all, at this point who is willing to do all those sweeping changes that if they had been implemented to begin with but now you don't dare change too much might have made the whole episode a 'non-problem'?]

I don't like to ask for much less than 5 mils, because tiny is tiny and always hard to work with. PCB houses don't seem to mind 5 mils. However, I have seen 2mil shops.

Not overall better shielding but the overall current loop's area has reduced. You can't reduce the distance along the PCB, but by reducing the separation between layers you HAVE reduced the area of the current's loop. THAT is where the reduction mainly comes from.

Good EMC design will give you exactly that, too. Better performance from less cross talk and less susceptibility to interference. So is a win-win situation.

My example was not to re-extract the clock, but rather re-transmit the clock Use buffers going OFF a board and use buffers going ONto a board, so why do people NOT use a buffer for distribution of a clock signal? Envision Clock generator here. driver sends 'information' down to a receiver elsewhere on the board. THAT receiver then supplies the reall energy into the chips down in that area. Doing that keeps the flow of energy running around all over the board way down, makes like 'islands' of activity. Much easier to keep that topology quiet versus one humongou chip driving stuff clear across the board! Think area of the current loop. With the first architecture you have three small loops of isolated regions of heavy currents, small currents across the board, heavy currents. But the other way you have just heavy currents everywhere! and large loops we're talking an additional 6 dB for the loop area and additional 6dB for the current magnitudes! Versus a 'free' drop of 12 dB. As in don't make the noise to begin with.

an EVEN harmonic where there should only be ODD hrmonics does NOT bode well. You may see a lot of variation in emanations based upon chip vendors, or even lot runs.

True, what you need is a 'snap' through transition region for digital to work well.

Just be glad you're below 1GHz, where magnetic material still works. Judiciously selected RF Beads KILL energy. That's what I mean by dissipation. I'm preaching to the choir now, because I can tell you have savvy with respect to EMC, but don't try to 'short' out energy. I've seen a lot of newbies put caps in to 'kill' the energy and all that does is squish it around. You really have to dissipate the energy to stomp on it.

Think like analog filtering. Go from high impedance to low impedance, to high impedance or low impedance [probably your sources] to high impedance to low impedance. All those mismatches prevent energy from flying around. Plus remember that free space is 377 ohms, that's why sometimes it takes a REALLY huge bead on a cable to stop it from emanating, because the bead has to get way up over 377. However, if the bead is placed right before a low impedance...

Shameless plug: I've done this stuff since 80's. We can discuss getting me more directly involved. Working together we do a review of the present implementation, consider all the principles involved, and potential 'gotchas' that might happen, where we can add the most effective 'insurance' Then cross our fingers. Your firm might get the unit to inexpensively slide right through EMC testing, you'd learn what I know and your firm would learn to use you in future product developments BEFORE damage occurs. A win-win situation. Contact me offline.

AGND

copy

or

REAL

I'll take some of that, please.

?-)

Sent, look forward to your comments.

If you like quantifying layout, you might also like this: I just finished the capability to combine .tran and .noise into a single analysis run on LTspice. Very useful for quantifying/gaining understanding of noise interacting with any non-linear process, like mixers, analog multipliers, oscillator's phase noise, etc Also, the technique produces realistic scope time waveforms with fuzz AND calibrated noise floors in the FFT.

There's an example of the technique [combining .tran and .noise into a single analysis run in what I call .tranoise] using Jim Thompson's OpAmp, MC1530, configured as a simple preamp posted to LTspice group BUT Helmut removed ALL my plots! so only the schematics are left, I guess.