OK, start with a PCB that has some silk screen text placed in the standard manner. Then add a silk screen logo derived from a BMP file using import-bmp.ulp . Viewing the PCB with _tsilk on shows both the text and the logo. BUT. Doing a CAM, the resulting .plc file DOES NOT HAVE THE LOGO!!!!!!!!!!!
Perhaps not the most suitable, but most of us manage to get our logos onto our PCBs (as well as cUL etc. logos) without undue drama.
Best regards, Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
if there was an automatic or manual conversion from a logo in bitmap data to Gerber vector data. I don't think the fotoplotter would handle a mix from bitmap and vector data. Fotoplotter of these days are using internal pixel data, but the resolution depends on the model used and will be different from resolution of the bitmap logo.
The UL (eg UR) logos and mfg logo the board makers put on the boards look pretty good. They are small and have some detail to them. I don't know if they are massaged at all, but it does not look to be a problem.
Layer 121, _tsilk is exactly what i used for the text and the logo; the CAM processor tab that generates the .plc file had layer 121 enabled.
I have done further investigation on this mess. Matters not what layer one uses (1, 2, 121, 200etc). Drawing a WIRE, it gets transferred by CAM down to 0.05mil (what Eagle calls zero). BUT....drawing a RECT, if the width or the length (ie one of its dimensions) is less than 1.0mil, it gets dropped. So, the Cam processor is flawed. Is there a fix?
Yeah; nobody is talking as how they got pasted (pun intended) on. If, say, they use Eagle and take the original logo to BMP converted by ULP to SCRipt to RECTangles. Or they use some other board program (Ivex WinBoard, etc). Or they have a secret way of taking a vector version of their logo and converting to Gerber (which then would not show in Eagle). Or....
I have done further investigation on this mess. Matters not what layer one uses (1, 2, 121, 200etc). Drawing a WIRE, it gets transferred by CAM down to 0.05mil (what Eagle calls zero). BUT....drawing a RECT, if the width or the length (ie one of its dimensions) is less than 1.0mil, it gets dropped. So, the Cam processor is flawed. Is there a fix?
Sorry, you'd have to consult the documentation (or google for no-doubt copious results) for your particular program- I don't use Eagle.
Hey, for my next startup I'm going to commission a logo that can be produced by multiple layers on a PCB (eg. copper + mask + overlay). (with due attention paid to the registration limitations of the overlay layer). Should be fun.
--sp
Best regards, Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
there are modern fotoplotters with fine pixel resolution, they may plot traces with a width of 1.0 mil. But this does not guarantee that these traces may be etched on a copper layer or printed with silk screen. Look for the smallest structures your pcb manufacturer is able to produce on copper or silk screen.
That's an overly pessimistic interpretation. The resolution that the supplier can typically reproduce is probably several times higher than the guaranteed no-breaks, no-shorts line-space minimum specification.
IOW imagine a 1mm square- you might be able to reproduce a 50 or 100um square "pixel" stuck in the middle of one side, but that doesn't mean that the supplier guarantees that a 50mm long trace 100um wide or traces spaced 100um apart will be electrically perfect.
Unless you want your beautiful corporate logo to come out all pixely-like (I suppose it might be blocky to begin with), it's best to err on the side of higher resolution. Maybe 200-300 DPI in the final size, which is around about 80-120um.
In the old days of computing, a high-res logo could actually slow down the layout software noticably, so one would tend to add it last, or turn it off during significant edits. Now that everyone has fast workstations, it doesn't seem to be noticable.
Back in the "good old daze" of TAPING a layout, homebrew fo double-sided (not PTH unless one was VERY brave),i would on occasion, repeatedly do 2mil, and 1mil was iffiy. As you may know, chemical purity, cleanliness, and techniques have improved slightly.
I never got much better than 15 mil feature size reliably with garage etching. You must be very talented to get 2 mil lines and spaces- more talented than many of the Asian PCB houses that offer 6 mils as standard and 4 mils at extra cost.
Of course if you're talking about millimeters rather than units of
0.001", that's somewhat easier. ;-)
--sp
Best regards, Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Ahh.. it was mils for the lines, but the smallest spacing was then in the region of 20 mils. I think that "pollution" from used etchant was the limiting factor.
Wow, getting the tape which was usually 3 mils thick minimum to stand up cleanly at 2 mils width is impressive. Or is there some confusion in the units?
We used to reduce it 2:1, I imagine some fine stuff would have been done 4:1.
Made it difficult to check the footprints.
Best regards, Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
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