Dot allowed as characters allowed in netlist?

Stuff happens. What is surprising though is that the ERC in the CAD didn't alert. Assuming that one of the notations was a mistake and happened only on one sheet that bus would have to be flagged as orphaned.

That's the smart way of doing it, where the schematic entry is a separate layer and acts as a "scrubber" between operator and netlist.

We just assign a net name to every offpage.

Changing Spice would also break things that worked last week.

That just happened to me with LTSpice. When it updates it seems to hose off custom symbols.

Am 14.03.2018 um 19:00 schrieb Kevin Aylward:

Those who do regression tests as part of their software qualification process, for example. I worked on the 10 million line operating software of a mixed signal wafer tester system and customers would have been quite upset when it started to make things "better" than the old HP from decades ago. That what has worked before must continue to do so. If not, it belongs into the bug list.

I admit that in the case of your hobbyist SuperSpice really no one would care a f*k.

And, what defines correct behavior: that's the brownish book from Berkeley. Other than in JT's phantasies there are no non- "Berkeley-related spice variants". The tail is wiggling the dog.

Gerhard

Quote "Robustness of Newton iteration depends on (1) having all circuit element I-V curves being continuous in value and slope and (2) all nonlinear elements being bypassed with capacitance so that the previous time step solution is a good starting point for the Newton iteration of the current time point. Conditions (1) and (2) are met by any physical circuit, but SPICE programs usually don't get this right because the semiconductive devices in Berkeley SPICE have discontinuities and these implementation errors have spilled over to pay-for SPICE implementations. These discontinuities do not occur in LTspice."

I haven't noticed that, but the XVII version has its own libraries and everything. It's a completely different thing from IV.

I am not going to upgrade anymore for a long time because when something like this breaks it creates a lot of unnecessary work. I can't see any reason why an update has to over-write a complete library file instead of just adding in the new stuff.

Unless it can. Altium toyed with that for a long time, of course nobody used it because their FPGA tools weren't useful compared to the manufacturer's.

No idea if there are higher priced tools with tighter integration.

Tim

That gets ugly when you have SDRAM busses.

I was just tweaking JL because he claims a perfect design review process. Apparently he doesn't use ERC.

How would adding fat black lines improve this?

Oh, that's *UGLY*! You might just as well forget schematics and just write the netlist manually.

It's a cropped screen capture. But it's a very nice schematic in real life.

How would you draw a DRAM except as a box with pins?

Show us your DRAM schematic.

A. It was a very long time ago.

B. We don't use busses any more.

and most important,

C. The guy is gone.

Wasn't there a drawing?

Millimeters are mm.

Isn't it rather the slick road that prevents stopping? How would the average driver be able to stop a car faster than with anti-lock brakes, given the same situation?

All those electronic helpers can of course induce a sense of invulnerability which cause more reckless driving, leading to situation in which they can't help you any more. In a rare cold and snowy spell around here recently I noticed that those 4-wheel assholes were driving like on a sunny summer day.

robert

No. In the US, mechanical engineers call millimeters "mils". What the electrical engineer calls a mil, they call a "thou". Since PCB manufacturing is arguably a cross-over discipline, all sorts of confusion is possible.

robert