Dividing a 32768 Hz crystal frequency

It's no big deal to lowpass a square wave into a pretty good sine. It's fun to Spice things like that, fiddle until it works.

Don't start with a 2nd order Sallen-Key! 3rd is OK. LC is nicely retro.

Given a binary counter and a hacked resistor DAC, I guess you can't reduce the 3rd harmonic, the big one.

Thanks, but the head of the thread is missing and I can't guess what went before.

Thank you. I will not continue this thread, with thanks to all.

tirsdag den 27. juni 2023 kl. 18.20.00 UTC+2 skrev John Larkin:

six steps can be ok

Consider a binary counter. The MSB is a square wave of freqency F, with third harmonic 3F.

The next bit is 2F with harmonic 6F.

I can't see how any linear-weighted combination of counter bits can cancel the 3F line.

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** Huh ??

Just to be clear, for a fixed frequency output you only need to build the schematic shown in fig 2. RT and C values of 10k and 10nF to give 1591 Hz.

...... Phil

It's even easier to low pass a "modified sine wave" -- --

- - - - - -- -- which you can get by switching between three voltages. The great virtue is that if the timing and the voltage are exactly right tghe thirtd harmonic contnet s exactl

That isn't how you do it. Feeding the square wave through a shift-register and using resistors hung on successive taps lets you set up a finite-impulse response filter.

They do have to go into an adder/subtractor op amp set up to generate the desired output.

For an infinite length shift register the optimal weighing is is the sinc function

which does change sign. Truncating it produces "Gibbs oscillations" which you can essentially eliminated by applying a raised cosine (Hamming) window to the finite length of shift register you actually use. The filter doesn't cut off quite as hard but it does cut off monotonicly.

You can kill the third harmonic pretty close to perfectly.

Many years ago, I ANDed a bunch of outputs from counter stages, and fed the result into the reset, to achieve division by some arbitrary integer. I was electronically naive [*] at the time, and what I did may have relied on the propagation delays to work properly. The application would not have been sensitive to the occasional glitch.

Or perhaps I was lucky enough to have bought a counter with a synchronous reset. Either way, it worked.

Sylvia

[*] OK, OK, you got me; even more electronically naive than now.

Actually, I think that it always works, sync or async.

Not necessarily: async reset can be fooled by the transient between-states values of a slow slewing or ripple-delayed clocked event. Using the gate output AT the main clock time should take you from N to zero, as long as gate and slew delays aren't bigger than a clock period.

I prefer to use a loadable counter, triggered by the carry out. Then there's no change to the logic when changing the divisor, just a change to the value loaded.

If you examine the timing of a ripple carry counter, the intermediate counts will always be less than the next count. It's because the clock input is falling edge triggered and the output has to be delayed from the clock input to each FF, so no false triggers on the upward counts. If the current count is 3, on the next input clock edge the count progression will be, 3 > 2 > 0 > 4.

A STM32 micro, so you can program whatever frequency you want to pass on.

In the ripple counter case, I recall that the terminal count transition is the first possible output of the AND gate, so it's safe to drive an async clear. If you decode state N, it divides by N.

Software DDS is fun too. Lots of micros have a 10 or 12-bit DAC which can be lowpass filtered into a nearly perfect sine. Interrupting at a few hundred KHz is easy nowadays.

A Pi Pico would make a cool general-purpose signal generator. There are a zillion possibilities for a product there, and would just need a bit of code.

I'm guessing that a 1 MHz interrupt rate could be supported on the DDS core. Covering the audio range would be easy.

I'll architect it if someone will code it.

It the counter is long enough and slow enough you may never get something that looks like "state N" on the outputs of a ripple counter - the low order bits have got past "state N" before the high order bits have got to it.

If it was that easy, Analog Devices wouldn't be selling their DDS chips any more.

sells for $2.12.

To make it work well, the code needs to be designed to minimize the jitter from interrupt source to triggering the DAC. I put the write as the first thing in the interrupt routine, then calculate the next sample.

Often there is inherent jitter in the interrupt response, but it depends on the details of the MCU chip.

LOL What's to architect?

The code would add the fset register to the phase accumulator and load the dac. No branches to alter the timing.

Nanoseconds wouldn't matter much. The trick in the Pi would to avoid cache misses.

Features, interfaces, specs.