I happened to come across this article:
"While it may be tempting to use a large power plane to simplify the routing of the VCC signals, this approach will most definitely lead to degraded system performance. By tying all of the supply voltages together at a large plane, it is impossible to prevent noise transfer from one pin to another."
While there's certainly some truth to the later sentence, I'm thinking that the tight (capacitive) coupling of a traditional power and ground plane largely attenuate the noise to begin with, and local bypass caps then kill off pretty much whatever remains when it bubbles up through a via near another power pin. Still, I have to assume the authors had some bad experience with power planes and found their star routing approach fixed the problem.
So the question is... does anyone here design their boards this way? Does it really help that much? Or did it possibly even make things worse?
The rest of the article has suggestions for reducing noise that are in-line with my experiences. In particular I've had some pretty badly behaving PLLs (very large PFD spurs), and suspect that their suggestion of power supply noise (rather than an inadequate loop filter) being the cause are likely.
---Joel