Discrete IF limiter for GPS Rx

Nov 14, 2010 8 Replies

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on the exact centre frequency; but around 20 MHz was my plan.



In the 80s and 90s, there were numerous FM IF chips; but they're all going obsolete now. The AD8306 is nice; but very expensive and is likely to pickup digital noise and other nasties on my board, all the way up to 1 GHz, because it has no selectivity. The LT6402 is differential, has fixed gain and allows a tuned circuit across the output. I was thinking about using a cascade of them; but this is a hobby project and I don't like QFN packages.



I was wondering how practical it might be to do this discretely using matched-pairs. I am talking about a cascade of long-tailed pairs with parallel tuned circuits between the collectors. This is a lot cheaper and simpler than a cascade of LT6402. Is that practical? Below is an LTSpice demo of what I have in mind. I would obviously include good PSU decoupling, a solid ground plane underneath and a balanced symmetrical layout.



The project is a single-conversion GPS receiver with fractional-N PLL generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA (with 2MHz BW SAW filter) before the mixer.



Any advice?



TIA



Version 4 SHEET 1 1764 680 WIRE 224 -96 64 -96 WIRE 464 -96 224 -96 WIRE 624 -96 464 -96 WIRE 848 -96 624 -96 WIRE 1008 -96 848 -96 WIRE 1216 -96 1008 -96 WIRE 1376 -96 1216 -96 WIRE 1472 -96 1376 -96 WIRE 64 -64 64 -96 WIRE 224 -64 224 -96 WIRE 464 -64 464 -96 WIRE 624 -64 624 -96 WIRE 848 -64 848 -96 WIRE 1008 -64 1008 -96 WIRE 1216 -64 1216 -96 WIRE 1376 -64 1376 -96 WIRE 144 48 -288 48 WIRE 224 48 224 16 WIRE 336 48 224 48 WIRE 544 48 336 48 WIRE 624 48 624 16 WIRE 720 48 624 48 WIRE 928 48 720 48 WIRE 1008 48 1008 16 WIRE 1088 48 1008 48 WIRE 1296 48 1088 48 WIRE 1376 48 1376 16 WIRE 1616 48 1376 48 WIRE 1760 48 1616 48 WIRE 224 64 224 48 WIRE 624 64 624 48 WIRE 1008 64 1008 48 WIRE 1376 64 1376 48 WIRE 64 112 64 16 WIRE 112 112 64 112 WIRE 144 112 144 48 WIRE 160 112 144 112 WIRE 464 112 464 16 WIRE 512 112 464 112 WIRE 544 112 544 48 WIRE 560 112 544 112 WIRE 848 112 848 16 WIRE 896 112 848 112 WIRE 928 112 928 48 WIRE 944 112 928 112 WIRE 1216 112 1216 16 WIRE 1264 112 1216 112 WIRE 1296 112 1296 48 WIRE 1312 112 1296 112 WIRE 64 128 64 112 WIRE 464 128 464 112 WIRE 848 128 848 112 WIRE 1216 128 1216 112 WIRE 0 176 -16 176 WIRE 112 176 112 112 WIRE 352 176 112 176 WIRE 400 176 352 176 WIRE 512 176 512 112 WIRE 736 176 512 176 WIRE 784 176 736 176 WIRE 896 176 896 112 WIRE 1104 176 896 176 WIRE 1152 176 1104 176 WIRE 1264 176 1264 112 WIRE 1616 176 1264 176 WIRE 1760 176 1616 176 WIRE 64 272 64 224 WIRE 144 272 64 272 WIRE 224 272 224 160 WIRE 224 272 144 272 WIRE 336 272 336 48 WIRE 336 272 288 272 WIRE 352 272 352 176 WIRE 400 272 352 272 WIRE 464 272 464 224 WIRE 544 272 464 272 WIRE 624 272 624 160 WIRE 624 272 544 272 WIRE 720 272 720 48 WIRE 720 272 672 272 WIRE 736 272 736 176 WIRE 784 272 736 272 WIRE 848 272 848 224 WIRE 928 272 848 272 WIRE 1008 272 1008 160 WIRE 1008 272 928 272 WIRE 1088 272 1088 48 WIRE 1088 272 1040 272 WIRE 1104 272 1104 176 WIRE 1152 272 1104 272 WIRE 1216 272 1216 224 WIRE 1296 272 1216 272 WIRE 1376 272 1376 160 WIRE 1376 272 1296 272 WIRE -288 336 -288 48 WIRE -16 336 -16 176 WIRE 144 336 144 272 WIRE 288 336 288 272 WIRE 304 336 288 336 WIRE 400 336 400 272 WIRE 400 336 384 336 WIRE 544 336 544 272 WIRE 672 336 672 272 WIRE 688 336 672 336 WIRE 784 336 784 272 WIRE 784 336 768 336 WIRE 928 336 928 272 WIRE 1040 336 1040 272 WIRE 1056 336 1040 336 WIRE 1152 336 1152 272 WIRE 1152 336 1136 336 WIRE 1296 336 1296 272 WIRE 1472 352 1472 -96 WIRE 288 448 288 336 WIRE 304 448 288 448 WIRE 400 448 400 336 WIRE 400 448 368 448 WIRE 672 448 672 336 WIRE 688 448 672 448 WIRE 784 448 784 336 WIRE 784 448 752 448 WIRE 1040 448 1040 336 WIRE 1056 448 1040 448 WIRE 1152 448 1152 336 WIRE 1152 448 1120 448 WIRE -288 496 -288 416 WIRE -16 496 -16 416 WIRE 144 496 144 416 WIRE 544 496 544 416 WIRE 928 496 928 416 WIRE 1296 496 1296 416 WIRE 1472 496 1472 432 FLAG 144 496 0 FLAG 544 496 0 FLAG 928 496 0 FLAG 1296 496 0 FLAG -16 496 0 FLAG -288 496 0 FLAG 1472 496 0 FLAG 1616 48 OUTP FLAG 1616 176 OUTN SYMBOL npn 0 128 R0 SYMATTR InstName Q1 SYMBOL npn 160 64 R0 SYMATTR InstName Q2 SYMBOL res 48 -80 R0 SYMATTR InstName R1 SYMATTR Value {RC} SYMBOL res 208 -80 R0 SYMATTR InstName R2 SYMATTR Value {RC} SYMBOL res 128 320 R0 SYMATTR InstName R3 SYMATTR Value {RE} SYMBOL npn 400 128 R0 SYMATTR InstName Q3 SYMBOL npn 560 64 R0 SYMATTR InstName Q4 SYMBOL res 448 -80 R0 SYMATTR InstName R4 SYMATTR Value {RC} SYMBOL res 608 -80 R0 SYMATTR InstName R5 SYMATTR Value {RC} SYMBOL res 528 320 R0 SYMATTR InstName R6 SYMATTR Value {RE} SYMBOL npn 784 128 R0 SYMATTR InstName Q5 SYMBOL npn 944 64 R0 SYMATTR InstName Q6 SYMBOL res 832 -80 R0 SYMATTR InstName R7 SYMATTR Value {RC} SYMBOL res 992 -80 R0 SYMATTR InstName R8 SYMATTR Value {RC} SYMBOL res 912 320 R0 SYMATTR InstName R9 SYMATTR Value {RE} SYMBOL npn 1152 128 R0 SYMATTR InstName Q7 SYMBOL npn 1312 64 R0 SYMATTR InstName Q8 SYMBOL res 1200 -80 R0 SYMATTR InstName R10 SYMATTR Value {RC} SYMBOL res 1360 -80 R0 SYMATTR InstName R11 SYMATTR Value {RC} SYMBOL res 1280 320 R0 SYMATTR InstName R12 SYMATTR Value {RE} SYMBOL ind 400 320 R90 WINDOW 0 5 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName L1 SYMATTR Value {L} SYMBOL cap 368 432 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value {C} SYMBOL ind 784 320 R90 WINDOW 0 5 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName L2 SYMATTR Value {L} SYMBOL cap 752 432 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C2 SYMATTR Value {C} SYMBOL ind 1152 320 R90 WINDOW 0 5 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName L3 SYMATTR Value {L} SYMBOL cap 1120 432 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C3 SYMATTR Value {C} SYMBOL voltage 1472 336 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 3.3 SYMBOL voltage -16 320 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 2 SYMBOL voltage -288 320 R0 WINDOW 123 24 132 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value SINE(2 10u 27e6) SYMATTR Value2 AC 1 TEXT -674 24 Left 0 !.tran 0 11u 10u 1n TEXT -672 -16 Left 0 !.param RC=270, RE=180, L=470n, C=100p


Are you really trying to run the nominally 1.023 MHz wide DSSS signal through the limiter ? That would make sense with exactly one DSSS sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different satellites and also other interference signals. The thermal noise for the 2 MHz bandwidth would most likely be stronger than the satellite signal, thus the limiter would be captured by noise, not by the signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to

1 kHz after proper low pass filtering.

It works, even if you limit _before_ despreading. I got the idea from here:

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and I did a C++ simulation (of 3 satellites @ -130 dBm each plus white gaussian noise @ -111 dBm) which seems to confirm it:

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see also:

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In fact, many GPS modules clip the bandpass signal before despreading. Albeit being unoptimal, this approach is pretty standard because of simplicity. That's why GPS is so easily jammed by CW interference.

The optimal approach would be limiting at some level before and after the despreading. The pre-limiting would clip the pulse interferrors before they get smeared.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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The standard non-rugged GPS receiver model is to bring the signal in from the antenna and run it through a 1-bit ADC*, then do all the processing in the digital domain. Running the signal through a limiting amp is immaterial to the behavior of the 1-bit ADC and simplifies the circuitry.

Like Vladimir says, this makes the signal susceptible to CW interference. But folks buy their GPS receivers anyway, so it must be all right -- right?

  • Yes, "Comparator" -- but the literature always calls it a "one-bit ADC, so that's what I'm doing, OK?"
Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html

The ARRL Handbook used to have limiting amplifiers in their "FM receivers" section. You might see if they have something.

There are also microwave amplifier chips that go down to that frequency range, and if I recall correctly some of them will go into limiting gracefully (some will be atrocious). That might be a fruitful place to look.

At a 20MHz IF frequency you could almost do this with 2N3904s; I don't think you need matched pairs if you're hard limiting, and a bit of emitter degeneration before the long tail will get you a lot of "matching".

Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html

The difference between a 1-bit ADC and a comparator is that the ADC output is properly synchronized to a clock. If you give the output of a comparator to a digital circuit, the designer may not know how to properly sample it, so you need a 1-bit ADC.

Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

BPSK

Carrier * Data (50bps) * SpreadingCode (1.023Mbps)

[snip]

Thanks for all the comments posted so far on this.

I've placed three versions of the LTSpice sim here

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Limiter2.asc was the original with parallel LC between collectors but not on the last stage Limiter4.asc has parallel LC on the last stage as well Limiter6.asc is an alternative approach with series LC between emitters

2 & 4 have different component values. If I add parallel LC at the output in version 2, it goes unstable. Maybe series LC between emitters is safer?

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