Digital line "blanking" effect (debounce?)

My tea hasn't kicked in yet this morning.

I'm trying to think of a circuit that has the following behavior, and I can't think how to do it with less than three chips.

Digital in and out:

The summary behavior is "follow the input as fast as possible, but don't switch any faster than 200kHz".

  • At rest, the output matches the input.
  • From rest, if the input changes the output immediately changes to match
  • For some interval set by the circuit, the output stays constant, no matter what the input does.
  • For the immediate case, the interval is ~250us
  • Once the interval is over, the output latches on the input; if it is different (again) then the blanking interval starts over again
  • Some (no more than -20, +100%) variation in the interval from rest vs. back-to-back blanking is probably acceptable.

Any thoughts? Trying to work through it just makes my brain cramp. (Actually, it makes me think fondly of 6-pin PIC parts).

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My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Reply to
Tim Wescott
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On Tue, 15 May 2012 11:32:19 -0500, Tim Wescott wrote:

Kind of like the logic on a refrigeration thermostat to prevent cycling too frequently.

Maybe a couple of 4011's connected something like this?

In __ o---+---------| \ __ | | )o--------------| \ | +--|__/ | )o----+----o Out | | +-|__/ | | | | | | +----------+ +--| ----------+------------+ | | | | | | | | | | + ----------+ | | | | | __ | | | | __ | +----| \ | | | __ +--| \ | | )o----+-------+ | +-| \ | )o--|-----------|__/ | | | | )o--|__/ | | | +-|__/ | | | | --- --- | C --- --- C | __ __ | | | / |- + / |-+ | +-----------o( | +--o( | | | \__|- + \__|------+ | | .-. .-. | | | | R | | | | R '-' '-' | | Vdd o-----+----+

(replace the RCs with something that treats the input diodes more gently if you prefer).

Reply to
Spehro Pefhany

I have to give in to some compulsive behaviour: NE555

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Reply to
Nico Coesel

Positive _and_ negative edge triggered one-shot, but configured as non-retriggerable during your 50usec interval?

At that speed why not use a 555 timer ?:-) ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Moto used to make a switch debounce part that was basically a shift register and a multi-input AND/NAND gate to a latch. Believe it was 6 deep. It wouldn't do the instanteous switch you want, it always delayed the output by 6 clocks, but it removed any glitch smaller than those six clocks...

Charlie

Reply to
Charlie E.

Sounds like a PLL to me.

Jamie

Reply to
Jamie

What is supposed to happen if the input is continuously switching faster than 200kHz? ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Yup. I've shown several such circuits here, using a 555. But it lacks Tim's "From rest, if the input changes the output immediately changes to match". It has a delay similar to the Moto debounce.

And Tim's timing specification is confusing... 200kHz and 250us... which is it? ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

You're kind. My specification was confused, not just confusing. I _said_ the caffeine hadn't kicked in yet.

Here, let me grab a CALCULATOR, which keeps track of the @#$% decimal point for me: 2.5us, which, since it's a half-period, works out to 200kHz max frequency.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Reply to
Tim Wescott

In that case, having the output switch at, or slightly below, 200kHz would be perfectly acceptable.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Reply to
Tim Wescott

So 1MHz input => 200kHz output ?? No synchronism? ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

You need 2 int's in software, one external on an IO pin, your external reference signal and one internally to maintain a square wave time constant with a high speed internal counter ported to a output pin.

Basically the external INT would query the internal hardware clock register(ISR) for a value lets say on the low side of the input pulse and then query it again on the high side of the input pulse. At the last query, this count value that has elapsed will then be used to program the internal interval counter that fires off an INT to toggle the output or if you want to directly program the hardware regs to have the counter directly toggle the output, etc..

Sounds like you're making a 180 degree tracking pulse?

Jamie

Reply to
Jamie

The desire is to roughly track the duty cycle of the output of a comparator, without switching some IGBTs so fast that they turn to smoke immediately (yes, IGBTs, 200kHz -- I know, I know).

Things are in closed loop, so in the event that the comparator output was chattering, slowing down the transitions to the IGBT gate would cause extra hysteresis in the controlled variable, but would still retain the correct duty cycle.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Reply to
Tim Wescott

Yes, it could be done in software. If the customer trusted the software not to tank at some crucial moment and slag some expensive electronics.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
Reply to
Tim Wescott

I agree. Spehro's approach, R-S with "qualifier" looks like the way to go. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Something like this...

formatting link

Requires "presence" of one state for >= 2.5us before it can be triggered to the other state.

Logic reduction is left for the digital guys. A mixed NAND/NOR R-S would likely simplify the steering. ...Jim Thompson

--

| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Poking around, timing from the output side, a major issue jumps out... the R/S flop is essentially level triggered... so more logic, or front-end it with something edge-triggered. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

=20

match

Immediate thought, state machine. Now i will read on and see what others thought.

?-)

Reply to
josephkk

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