Dielectric biasing question

Jun 18, 2008 1 Replies

I have a differential pair used for high speed digital stuff. It needs to be ac coupled to the receiver. The signals can be on some common-mode voltage on the order of 0 to



+3V. The question is where to put the ac coupling caps? Near where the signal enters the board, or near the chip's inputs?

Does the DC level bias adversely affect the high frequency performance (loss) of the material underneath the traces? I suppose at 3KV there might be something but at 3v?



Anyone? John?


No 3VDC will have no effect on the PWB material.

But.. I prefer near the chip inputs so that any DC leakage or short on the PWB does not apply DC into the chip..

Mark

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