Dear Group, Please contact if you are interested in the DFT job listed below. Regards, Brent snipped-for-privacy@yahoo.com
Senior DFT Methodologies Engineer Location Plano, Texas (next to Dallas) Salary $110K- $125K Position Description
Develop, document and implement DFT methodologies for the Structured Digital Products Business unit =B7 Memory BIST Algorithm Development, Support & Documentation =B7 Define, support and document JTAG implementation standards and methods =B7 Define, support and document DFT strategies for IP and transceivers =B7 Develop, support and document strategies for delay fault testing =B7 Define and drive DFT software tool strategy, both industry standard and internally developed
- Interface with 3rd party vendors and CAD department
- Contribute to future software vendor selection
- Define internal/custom software & script needs and work with CAD on implementation =B7 Ownership for all aspects of the DFT strategies for the Business Units Product Lines Position Requirements =B7 3+ years in ASIC Design =B7 3+ years in DFT Methodology/Implementation =B7 7+ years total Industry (ASIC) Experience =B7 Memory BIST Algorithm development and implementation =B7 At-speed, Diagnostic for Failure Analysis =B7 JTAG Boundry Scan Design & implementation =B7 IC Parametric test methods and implementation =B7 Transition & Path delay testing =B7 Scan testing methods =B7 Low pin-count test methods =B7 IP test methods & implementation =B7 PLL, DLL, A/D, D/A, Transceivers: LVDS, PCI-e, XAUI, USB, SPI =B7 Experience with industry standard DFT tools such as Synopsys or Mentor (Synopsys preferred) =B7 Excellent written and verbal communication skills in English =B7 Ability to travel domestically and internationally as needed (15-20%)