Detecting the peak value

Technically, he needs one good resistor (spring for a Vishay 0.01%, or a cheaper Susumu 0.05% part) and a decent frequency counter. If you trust your ADC linearity (and the charge distribution ones are very good) you can bootstrap a whole chain of other parts off those two.

I guess you could buy one new resistor every year, and check your counter against WWV or GPS, and stay "certified."

John

That was the plan - I have a hundred or so Vishay S102Cs so I figured that I might as well use a couple.

What would the magnitude of these errors be? Enough to matter?

Hal

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Hi,

I am attaching two new drawings to show what I want. I do not know about accuracy but i would as say as much as accurate as possible.

First link is as follows

Second link is as follows

I want to sample the peak value of the sine wave by using ADC (sampling rate 200ksps). I want to sample the peak value of the sine wave at the rising edge or the falling edge of the square wave that you can see in the diagram. The edges will trigger the ADC and ADC will sample that edge. The ADC can not sample the negative values as shown in the diagram. I did not mention the circuitry that can add offset to the input signal and make it all positive.

The questions are

1. Is there any way other than RC circuit to get the peak sample of the sine wave at the rising and falling edge?
2. Whats the difference between in this case between using the High pass and low pass filter?
3. How a PLL can help in this case?
4. Any advice about choosing the right ADC?
5. I tested the suggested high pass filter using the 220pF and 7.6kOhm resistor and found that the edge is occuring at the right spot in pspice than the low pass filter.

Thanks John

That's more or less the circuit I was thinking about - I had been playing with it in SPICE and it _seemed_ to have the required linearity, but I wasn't sure. I'll probably have 3 ranges (50ma, 200ua, 1 ua - each a dedicated source). I was also thinking about choppers, although still looking at specs - especially for the 1ua range. All voltages and currents are drived from a buffered and filtered internal reference (MAX6341), I'll have +- 5v available, +-12 (or +12) if needed for the op-amps. Any special considerations using the applicable portion of the above circuit for these current ranges? Anything special to consider in the MOSFET?

Thanks

Hal

I made what I thought was a really nice circuit for measuring capacitance, relying only on a known precision resistance and a stable frequency. (Which are the two most easily obtained precision quantities in electronics I think).

It uses a (gulp) charge pump :)

Basically you use a dual low charge injection analog switch to alternately switch Cx across a reference voltage, then dump the charge into a BFC. This is then connected to an opamp virtual earth. The feedback resistor is the precision 0.01% resistor, and your ADC uses the same Vref so it's precise value doesn't matter.

It's the same principle as Fig 12a in Linear Technology AN03, with the

Trust, but verify. If he's going for ".02% on all functions", he'd better have a pretty damned good ADC, and everything else, right down to the amplifiers. Your .01%, or .05%, resistor just ate pretty far into his error budget. ;-)

He's babbling, as usual. The mosfet current source I posted has zero errors from those effects.

John

I don't think such an active current mirror will hold up to your 0.1% accuracy... aforementioned channel-length modulation. ...Jim Thompson

Stepping into it again? Your loop will need a much wider bandwidth than the ramp rate to counter channel-length modulation... thus I doubt 0.1%. ...Jim Thompson

I don't babble, but you definitely bloviate :-) ...Jim Thompson

My differentiator finds the peaks. You can use that to trigger the sampler of the ADC, or use the count-up/count-down scheme that John Fields demonstrated. ...Jim Thompson

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If you are already employing a ADC, then I assume you are using some sort of uC unit? That being the case, you simply use +/- slope detection while monitoring the ADC value in a high speed sample rate.

All one needs to do is first use the base line values to determine the direction of the slope, set a flag and when that direction changes or remains the same as the last reading, you take the last reading and average with the current reading.. that should give you a close value to work with.

If you are not working with uC's, then why the ADC ?. One could use the square wave results of what every one has suggested to you thus far and employ edge triggering, that will operate a sample and hold circuit to record the peak voltage, one circuit for each polarity via the +/- transitions of the square wave. These value at some point can then be used to drive other functions.

Seems like an eliminatory circuit me. Did something similar years ago using 4066's and FET input op amps for sample and hold to drive a ADC in the joy stick port of a Commodore 64 to receive weather FAX.

Oh well.

Don't pay no mind to me, I'm just a poor inbred person from Maine, where every one is related.

Jamie.

Wish my memory or filing system was better, there's a circuit I saw that used an opamp to supply fixed voltage offset to an RC to get linear cap charging. It's related to capacitor multiplier circuits and ramp generators.

Constant voltage across resistor == constant current into cap over the working range of the opamps.

But I can't find the thing, does it ring a bell?

Grant.

Which we'll never be able to disprove, because John "The Bloviator" Larkin never gives values or part names.

However, for you people trying to learn, the very network around the power FET, needed for stability (capacitive load on OpAmp) allows channel-length modulation to remain.

Tutorial on channel-length modulation to follow...

Can't do it tonight... already had two "1964" martinis at Benihana ;-)

I'll also demonstrate the current-source-less approach I previously alluded to.

For technical expertise you can always count on Jim Thompson ® ...Jim Thompson

Aiming for 1 or 2 percent is far easier for home built stuff, and buying precision resistors is one way to get a cheap 'standard'.

Plus crystal-locked frequencies, derive from those, I don't see a problem. I've worked with transfer standards in the past, can get expensive to add good accuracy.

Grant.

But he was aiming for .02%. It would be a big enough job at 1%, but five times better is a *lot* more than five times harder.

That gets you one calibration standard. You're going to need more for LCR.

And how does one overcome that?

I can't see a DC effect (not saying there isn't one) because steady state it looks like the source sense resistor is seeing the drain current, disregarding gate leakage.

I can see there might be a dV/dt related issue due to drain-gate capacitance, is this what you're talking about?

All I can see is that there might be a voltage compliance change due to the effect you mention.

You published similar circuit, CurrentSourceConceptual.pdf four years ago, but I didn't check if there's any related discussion.

Grant.

But never claimed to be good to 0.1% ...Jim Thompson