Defect in Analog Devices Spice model for the AD734

Been there. Where do you think the examples came from? ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs
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Part of the problem is op amps are surrounded by a bunch of components, so snaking a wire to the power pins can get tricky. I usually label the supply voltages and simply tag the power pins with the appropriate label.

For example, +5 takes up very little room, and you can clearly tell when it is not connected. There is a little square pin underneath the label that disappears when it is properly connected. An ordinary wire does not have the square pin so you can't see if it is connected as easily.

Another method to help eliminate errors is to label *EVERY NODE* in the circuit. This is crucial.

For example, if you add two resistors in series, the node that connects them may be N002. You can use that label to plot a waveform or make a measurement.

However, if you add two more components in series somewhere else, the node that connects them becomes N002, and the previous node becomes N003.

Your waveforms now refer to a different part of the circuit, and it may be very difficult to see what went wrong.

But if you label every node, this can't happen.

Instead of trying to invent new node names, I simply use two adjoining components for the names. For example, R1C1, D2C4, L1C3, etc.

For active devices, I use Q1B, Q1C, Q1E for the base, emitter and collector. The device names take precedence over component names. This makes it much easier to find the desired node in the schematic.

Further examples are M1G, M1D, M1S for gate, drain and source.

Op amps get U1P for the positive input, U1N for the negative input, and U1O for the output.

Logic elements get U1X, U1Y for the inputs, U1A for the outputs.

When you copy part of a circuit to use somewhere else, the node names remain the same but the component values change. Then it is very easy to tell which names need to be updated since they won't correspond to the new component names.

This solves the problem of using signal names for the nodes. It may be difficult to tell which signal names need to be changed, and if you leave the wrong ones connected, your circuit will do strange things.

These simple tricks can save a lot of time wasted trying to track down analysis problems.

Reply to
Tom Swift

You have to be careful in naming stuff, though--if you call it VDD and not +3.3V, for instance, it'll probably survive changes better. ;)

Yikes. Must be a pretty simple circuit!

Seems like a bit of an OCD solution, though. Just clicking the node you want a couple of times fixes it.

If you spend a great deal of time sweating over LTspice, I can see where that might be worthwhile, but it looks like a lot of extra work to me.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

User choice. I like to be explicit, especially when there are several supply voltages.

It doesn't take very long, and you can check the waveforms at every node much easier. It is even more helpful in complicated circuits where you can easily get lost trying to troubleshoot.

It's not clear what you mean. Once you have defined a waveform using a node number, or used the .measure command, you are hosed when you change the circuit.

Then good luck trying to find the original node where you wanted to take the measurement.

It doesn't matter how much time you spend on LTspice. A simple mistake can cost you a lot more time. You see this fairly often in this newsgroup, and especially in the Yahoo LTspice forum.

It's not really that much work. Press F4, enter three or four characters, plop it on the node. Done.

Why not eliminate these problems at the beginning. It really helps eliminate time wasted on problems that should not have happened in the first place.

Reply to
Tom Swift

I started out with Spice that didn't have schematic entry, thus I drew schematics by pencil, numbered the nodes, then made a netlist with a text editor (first using a VAX780, then under DOS).

It was such a royal pain to keep track of version changes that I had my son Aaron (when he was a teenager... he's now 45 :-) write me a version handler that saved as *.cir.01, *.cir.02 etc. Also saved the

*.dat files that way, thus it was easy to back up under a munged change.

I do agree with Tom Swift on one point... naming nodes you want to repeatedly observe forces the simulator to retain that name from run-to-run thus avoiding the simulator renumbering nodes every time there's a recompile. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

If you have multiple supplies, calling them all "Vdd" causes problems. ;-)

I try to name all nets in a schematic. It makes probing the layout much easier.

Reply to
krw

Hmm. Normally I don't spend that much time on a given simulation--there are usually only a couple of things I need to find out that SPICE can tell me.

I might spend more effort on an all-discrete design, but IME most IC models give only an impressionistic view of actual chip behaviour, so it's hardly worth the effort.

Cheers

Phil Hobbs

Reply to
Phil Hobbs

I probably use SPICE for even less than you because I don't give the models that much credit. Even the discrete models suck. It's too easy to trust the simulation. OTOH, when I did chip design I relied on SPICE (well, ASTAP at the time). IBMs models were superb.

I was referring to the board schematic, though. Naming all the nets makes reviewing the layout much easier. Though not all net names get printed on the schematic, it's easier to deal with them than a thousand similar strings.

Reply to
krw

Here are some examples where simulation can be very valuable.

  1. Use universalopamp2 and set the voltage gain, GBW and slew rate to see the effect on open and closed loop response, gain and phase margin. This can help you decide on how much performance is needed in the op amp and how much money to spend on one.

I'm sure you could do this in your head, but most people need help and LTspice does a good job. It gets more complicated when there are multiple op amps involved.

  1. Check pll loop damping and step response with variations in op amp gan and bandwidth, as above.

  1. Develop new circuit configurations and check the response before going to breadboard. Pencil and paper is a good place to start, but LTspice gives a much better picture of what is going on and where the weak points are.

You used this technique yourself when you developed a calibrator for one of your wideband circuits. You found that a tiny amount of series inductance was enough to destroy the performance you were seeking, and ended up putting a bunch of parts in parallel to reduce the inductance.

  1. Document circuit response for troubleshooting in manufacturing. Techs can easily see how the circuit is supposed to work and check waveforms at different points. Then compare with the results on a defective pcb to see what needs to be replaced to solve the problem. Finally, check the repaired circuit to verify it performs as expected.

I think it would be professional to include node names at every node to help the techs find their way around the circuit.

There are many more examples, but I think you will find most engineers feel that LTspice simulation is a valuable tool. Until you get screwed over by sloppy or nonexistent node names.

Reply to
Tom Swift

This is a bit garbled. It should read

  1. Use universalopamp2 and set the voltage gain, GBW and slew rate to see the effect on open loop gain and phase margin and the effect on closed loop response.
Reply to
Tom Swift

AD734 running with a current output - see Figure 25 on page 13 of the Rev E AD734 data sheet

4.pdf

current output limits at something between +200uA and +280uA.

.

did the voltage at the W and Z1 outputs get high enough to be interesting.

A at 15k.

n to -350uA.

ts clamped a lot higher, at about +800uA, when the negative currents were g etting down to -2.4mA.

4 Spice model (which would interest Jim Thompson, who wants to sell Analog Devices better Spice models).

about +/-10mA output current limits (as it does on page 13).

ng. Any advice will be gratefully received. I probably should have raised t his with Analog Devices directly, but the price they charge for the AD734 m eans that they can't be selling many of them, which doesn't suggest that I' d get a prompt response.

n my circuit diagram - a connection to +15V seems to have been edited out a t some point and the circuit was getting it's positive power supply from it s inputs, making the model inconveniently realistic - I've had that happen on real circuits, and it can take a while to work out what's going wrong.

I have always felt that text input based SPICE versions(HSPICE, NGSPICE) ar e so much better than GUI input based SPICE versions(LTSPICE) The tiniest error in the text netlist input causes the simulation engine to crash, forcing the oser to ensure that the initial input netlist is correct. I believe that LTSPICE also allows text file input. I have used the BSIM 4.6.5 sub-micron device models in netlists that are approximately 750 - 900 lines long, with both HSPICE and NGSPICE, with only a few whimpers of protest initially, but absolutely no issues afterwards.

Reply to
dakupoto

Sure thing, I didn't intend to imply otherwise. I do the math first, though , whenever feasible.

The things that are hard to do by hand are often also things that SPICE mod els are bad at, e.g. overload recovery and CM slew distortion.

There are things where simulation is really the only cost-effective method, e.g. checking the strictly-linear response of an active filter made with n on-ideal components, or (what I'm often interested in) looking at the sensi tivity of a high-frequency and/or high-Z circuit to strays.

I don't trust behavioural IC models at all. There are too many noiseless op amps with zero input capacitance and perfectly-clean slew limiting out the re in spiceland.

Transistor models are much better--I built a BFP640/pHEMT cascode TIA a cou ple of months ago. Simulation correctly predicted the collector current whe re it started oscillating, within about 10%, and got the frequency more or ledd right too (about 6 GHz). You do have to put in realistic strays, thoug h.

Cheers

Phil Hobbs

Reply to
Phil Hobbs

Text entry of netlists is barbaric. Imagine a 1000-line netlist to sim some part of a product. Imagine needing to revisit it after a year or two of inactivity. What are you going to do to figure it out? Read it and try to draw the schematic!

Sure, Spice will catch you if you mistype "V10", but LT Spice won't misspell V10 when it saves a netlist.

I can enter a presentation-quality LT Spice schematic in a fraction of the time I could type a netlist. I can reopen it a year later and see what's there in seconds. And it has a nice parts library, and HELP, right there in plain sight.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Pull out the D-sized schematic from your archives. Don't worry, it's wrapped around the matching card deck.

I thought you were still into velum schematics.

Reply to
krw

All our schematics are scaled for B size, so our digital copier can print or scan them. I can open a 20 year old PADS schematic or layout, from the company server, instantly, with the latest PADS software. I don't think we've ever lost a schematic or layout or BOM in about 30 years of designing and selling stuff.

I draw my original designs on vellum, decorated with design notes, equations, rev notes, whatever. I like to draw. My CAD folks enter them into PADS and we iterate an review from there. I tend to lose little scraps of paper, but I never lose a D-size vellum.

Funny, but my newest engineering hire likes to draw, too. My layout people prefer to enter the schematics from hand-drawn input, so they can follow their own standards. It all works.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Ok, thanks for the response. I just dropped in to offer some ideas on error-proofing LTspice. Your comments have been interesting, but I gotta get back to work. Lots of circuits to build and put into service.

Thanks

Reply to
Tom Swift

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