The +1 core current is remarkably low, around 70 mA. The bank currents are higher, but they don't affect prop delay like the core supply.
I'm currently using an ST1L08 regulator, which is remarkably accurate on voltage. Like a few tenths of a per cent, which includes the divider resistors... which just happen to be identical in this case.
-- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
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This is a bit nuts. If you want a precisely timed edge, or precisely timed edges , you get them out of ECLinPS, which doesn't mess up it's voltage rai l to produce context-dependent jitter.
By all means use the programmable part to select the relevant ECLinPS outpu t when you want it to be active, but then resynchronise the edge to the nea rest ECL clock edge, rather than relying on poorly specified delays inside the programmable part. If you want fine granularity on the timing use the
The actual delay through the part does vary a bit with temperature, but you can auto-calibrate it out every few minutes if you have to.
-- Bill Sloman, Sydney
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