Custom semi-custom or what other ideas.

If you need less than 100ku, hybrid might be a better idea.

That would be huge.

MooseFET should contact me to discuss.

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
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 I love to cook with wine     Sometimes I even put it in the food

On a sunny day (Thu, 30 Jul 2009 17:47:20 -0700 (PDT)) it happened MooseFET wrote in :

With that much budget why bother doing anything at all?

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The customer(s) is willing to pay for smaller lighter and lower power. They don't like me for my good looks.

On a sunny day (Fri, 31 Jul 2009 06:51:56 -0700 (PDT)) it happened MooseFET wrote in :

Ok, but ASIC is very very expensive, makes no sense to me for a low quantity, unless it is NASA and a space mission or something like that. So, as he has a couple of million available to burn, why not go to Acapulco and be happy with it?

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So, what is the projected qty? You might need big die and custom fab processes. They (the fab house) need to know how committed you are.

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Some people say that I should be committed, but that's another story. :)

I can see many thousands to 100K depending on the price per unit once the NRE is covered.

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The first 10Ku costs 90% of 100Ku. Additional units cost like peanuts

I have another customer that might be interested in sharing NRE. Production will be in the Shanghai area.

How about the interface structure? For your 12x12 D2A bits, do you want parallel or serial interface. What is your data rate?

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I don't just want to put the DACs on it but I'll take the idea and explore it a little.

The digital interface consists of an 8 bit data bus and an N bit address bus along with CS/ and WR/ signals.

The processor writes the bottom 8 bits with the A0 low and then the upper 4 with the A0 high. It always finishes one pair of writes before starting another so only one holding register is needed.

Not all of the DACs are doing the same thing:

1 DAC is ideally more like a 16 bit one. Its output must be low noise. It must have glitch free updating. 3 DACs are doing a 4 quadrant multiply by an AC signal in the 50KHz to 500KHz band.

2 DACs are each constructing a waveform in the DC to 5KHz band that needs to be free of any noise above 30KHz.

3 DACs are making a near DC value that must be low noise.

There are some other bits that aren't really DACs in the normal sense of the word that do things I can't tell you about.

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So, rhe DACs are really analog computing blocks. Are you putting the processor (more likely a dsp) on the chip as well?

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It had come up but that would drive the chip to be more expensive and harder to design. The low noise requirement become real trouble when you have the current pulses of the CPU section in the picture.

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Yes, integrated processor core increases NRE costs, but decreases unit costs. In addition to lower external connections, they can probably share some address decoders and register file. The processor core can be standard IP licensed block. While it increase mask count, it decrease pad areas and wire bonding costs.

You are right. There must be separate power pins for the digital and analog parts, and isolated externally. But this requirement is the same for single or multiple chips.

Do you have a working prototype with discrete parts? There is enuogh fun to build this with individual chips. Wafer integration will double the fun.

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I am on my way towards having the thing made out of off the shelf chips etc.

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I know a handful of people who can build this type of chip. Perhaps you should come for a visit. I can meet you in Taiwan (hq), Hong Kong (sale) or Shanghai (production). I can be reached at 86-13723404205.

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Production in China may be a problem. I am going to check with the legal folks about export regulations.