cooling a SOT23 opamp

CHECK: a top side thermal pour will help a lot; tie to that pin with a wider than standard trace (2 mil iso to all else is nice),copper pour under the part and (if you can) make that pad at least 10 mils beyond the part outline. Then right underneath the part (12 mil PC thickness max) another full pad same size as the top heat spreader. Ditto on the bottom. Thermal vias are a bitchy tradeoff. If you can manage a hole that is "just" small enough to allow/accept/attract solder fill, then you get the advantage of thermal conductivity of metal,without undue decrease of the PCB integrity (careful on spacing...).

I'll probably put two vias under the part and one outside, all close to pin 2. They would be pretty small, masked, unpasted, and won't fill with solder. Figure maybe 30 K/w each to an internal (layer 3) -12 plane. That's 10 K/w for the vias, not bad when I'm trying to pull down 325 K/w.

FYI, never mask via-in-pad. That traps gas, which bubbles up under the solder, leaving voids, or worse.

If The Brat has handy copies of relevant IPC standards (hey, 782A and 7351 are available for free online, now! -- 2221A I don't think is supposed to be, but can be found nonetheless), she probably knows this already.

In my experience, 12 mil i.d. (0.3mm) vias don't wick much if at all, especially with RoHS processes. In principle, you can put in as many of those as you like. Though for such a small chip, two is probably about all you can get, given board specs (standard usually being >= 8 mil via i.d., > 10 mil hole to hole edge clearance, 5 mil minimum annular ring).

Also, larger pads are almost always fine, but be careful it doesn't float up from excess solder. You can fake it just as well, using fat traces or pours with no thermal relief (or leave the relief in, it'll only ever drop a degree or two anyway), with the bonus that you don't have to customize a footprint.

Tim

We'd be putting the vias in copper pours, not pads.

If we intend to solder something, we don't mask it. And vice versa.

OK, I tried it:

If this is believable, theta is around 120 K/w, as compared to the data sheet value of 325. I should be able to get ballpark 200 in real life, not radically worse than an SO8.

The SMD-in-wave soldering process employed epoxy 'dots' to fix components. Some body sizes no longer anticipate this, so it might not be compatible with reflow techniques.

SOT23/TO236AA, SOT143/TO253 did,(minimum 0.0005 body to mounting surface) but later drawings for six pin parts (SC74/MO178) or reduced size versions didn't (0.0 minimum).

Although the interface material is higher impedance than copper, the shorter distance and larger x-section does reduce Rth.

An inverted chip base doesn't help.

Adding this process step for just one dot obviously has it's disadvantages.

RL

An epoxy dot on a copper pour, under the chip, would probably reduce theta a bunch. But that's another messy process step and would complicate rework. I think we'll use two of the LM8261s working in parallel, with their V- pins nailed to a power pour. That will let give us respectable product specs (namely how much power our synthesized resistor can absorb) and will be the normal pick-and-place process.

LM8261 is a cool part, a high voltage RRIO opamp that's fast, high current, and tolerates any capacitive load. But it's not cheap. I show $1.25 in our data base.