Question for the RF-knowledgeable: I intend to use AD9510 for clock distribution, as it has fery low additive phase noise. My problem is, according to the datasheet performance is degraded if input exceeds 2 V peak-to-peak, and the low jitter TCXO I am considering has the typical either 3.3 V or 5 V output. Someone suggested I use a 2:1 or 3:1 balun, but I'm concerned about bandwidth, since the clock is square wave output (because the AD9510 datasheet says it needs high slew rate on the inputs for optimal performance). I'm also not sure how to handle transmission line effects. With a PCB track impedance is easy to control, and I normally use series termination resistors at the source on high speed lines to get a decent waveform, but I'm not sure what inserting a balun will do, how to choose the balun, and where to locate it for best performance (at the clock or at the distribution IC's input). The TCXO I'm using has about -110 dB phase noise at 10 Hz offset from the fundamental of 24 MHz, and I'd like to not get more than 5 dB increase from the overall distribution circuit--transformer+AD9510. What's the best approach?
- posted
16 years ago