Can Pulse Mismatch in Synchronous Buck Converter kill the FET?

- M
- Myauk
  
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posted
12 years ago

Fri, Jun 17, 2011 6:45 AM

We are testing a synchronous converter section of PCBA over ICT (ISL95870B), and whenever we probed it in ICT Station for testing the high side FET was always burnt. It seems to be a DFT issue.

Any failure scenarios? Please refer to page 4, figure 7 of this document

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and can anyone suggest me what are the critical points which should never be loaded by test pins and if loaded it could fail?

Regards

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- W
- Wanderer
  
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Vote on answer
posted
12 years ago

Fri, Jun 17, 2011 6:39 PM

The major source of losses in the high side transistor of a synchronous buck converter are switching losses. Switching losses are basically the time to turn the transistors on and off, which is limited by the gate capacitance of the transistor. My guess is your probes are increasing the capacitance of the high side gate for a long enough time to cause the transistor to over heat.

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