Hi,
I'm having problems with measuring (through simulation) values for K and Ve, in order that I can then use those values to design with in a process which I have the design kit for. Something has gone wrong though because when I try and use these values to design a differential amplifier (following the methods in Sansens book "Analog Design Essentials"), the gain and bandwidth I get are just rubbish - nothing to do with the intended specifications I calculated device sizes for. Can anyone tell me whether my procedure for calculating K and Ve is sensible? It is as follows:
To calculate K, I just used a single nmos transistor (w=1u l=1u) with a 50k resistor from vdd to drain. Then K'=Id/((Vgs-Vt)^2), and my results for a sweep of vin from 0.75v -> 1.6V gave me a decaying exponential with a knee at about vin=0.9v (ie. beyond (vgs-vt)~0.9V, K' is flattish). So I have a range of K' values to use depending on what the vgs-vt is.
To calculate Ve, I found an expression rds=VeL/(Ids), so I used the same circuit as above but stepped Vin from 0.75V to 1.3V. My simulator tells me the gds (=1/rds) at each Vin, so I just computed Ve=rds*Ids, to get a result in Volts/micron. Plotting the results, I get a parabola rising from Ve=30 at Vin=0.75, and peaking at Ve=52 at Vin=1.2V (then decaying after Vin=1.2).
Part of my problem could be because my Vt value seems to change a little for some reason, according to my simulators output. I've connected the bulk to source so I don't know why this is. I'm not sure if I'm doing something else fundamentally wrong though.
Thanks for any insight on this,
Oh, and thanks for the replys to my post the other day on what a Gm stage is, that cleared some things up!
Ted