Bias Calculations (Bootstrapped?)

"Warren"

** Bootstrapping involves signals.

C12 removes any signal from the game leaving only the DC bias.

.... Phil

Phil Allison expounded in news:90n6rgFe2lU1 @mid.individual.net:

since

bias.

You're right.

My next question then is why use this particular biasing arrangement? I.e. why bother with negative DC feedback using R16 (22k)?

Wouldn't a voltage divider to bias the base of Q3 be stable enough? The input & output is capacitively coupled.

Warren

On Apr 14, 1:01=A0pm, Warren wrote:

Ok folks- I figured it out for myself. Now I won't forget the lesson. :)

This arrangement allows you to configure your input impedance, regardless of any voltage divider bias requirement you might otherwise have used.

In fact, I liked the idea so much I've now used it in my current transistor based phase shift oscillator design. I wanted to keep its RC constant high (at the base). This meant keeping R high (100k). I've pasted the LTspice file for it below.

If I had arranged that through a voltage divider instead (like my upstream version) the bias might not be as stiff as it should be.

In the circuit below, I also purposely skimped on the value of C7, so that at the low end (2Hz), it wouldn't bypass as much. Thus providing some added negative feedback at the low end. I believe this helps the sine purity some, though the two LP filters on the output are still needed.

Warren

Version 4 SHEET 1 1204 680 WIRE 480 -144 -80 -144 WIRE 944 -144 480 -144 WIRE 368 -96 -272 -96 WIRE 480 -96 480 -144 WIRE -272 -64 -272 -96 WIRE 416 -48 0 -48 WIRE -272 48 -272 16 WIRE -192 48 -272 48 WIRE 480 48 480 0 WIRE 480 48 -112 48 WIRE 512 48 480 48 WIRE 624 48 592 48 WIRE 656 48 624 48 WIRE 768 48 736 48 WIRE 816 48 768 48 WIRE -80 112 -80 -144 WIRE -80 128 -80 112 WIRE -272 144 -272 48 WIRE -112 144 -272 144 WIRE 0 160 0 -48 WIRE 0 160 -48 160 WIRE 48 160 0 160 WIRE 128 160 112 160 WIRE 160 160 128 160 WIRE 176 160 160 160 WIRE 240 160 224 160 WIRE 272 160 240 160 WIRE 288 160 272 160 WIRE 368 160 368 -96 WIRE 368 160 336 160 WIRE 944 160 944 -144 WIRE -112 176 -272 176 WIRE 480 176 480 48 WIRE 624 176 624 48 WIRE 768 176 768 48 WIRE -80 208 -80 192 WIRE -272 224 -272 176 WIRE 624 240 624 224 WIRE 128 256 128 160 WIRE 240 256 240 160 WIRE 944 288 944 240 WIRE 1040 288 944 288 WIRE 1040 320 1040 288 WIRE 944 336 944 288 WIRE 128 384 128 336 WIRE 240 384 240 336 WIRE -80 496 -80 208 WIRE 128 496 128 464 WIRE 128 496 -80 496 WIRE 240 496 240 464 WIRE 240 496 128 496 WIRE 480 496 480 256 WIRE 480 496 240 496 WIRE 624 496 624 240 WIRE 624 496 480 496 WIRE 768 496 768 240 WIRE 768 496 624 496 WIRE 944 496 944 416 WIRE 944 496 768 496 FLAG 1040 320 0 FLAG -272 224 0 FLAG 816 48 Out IOPIN 816 48 Out SYMBOL Misc\\battery 944 144 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12V SYMBOL Misc\\battery 944 320 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 12V SYMBOL res 112 368 R0 SYMATTR InstName R1 SYMATTR Value 130 SYMBOL res 224 368 R0 SYMATTR InstName R2 SYMATTR Value 130 SYMBOL cap 48 176 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C1 SYMATTR Value 10uF SYMBOL cap 160 176 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C2 SYMATTR Value 15uF SYMBOL cap 272 176 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C3 SYMATTR Value 10uF SYMBOL res -208 64 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R4 SYMATTR Value 320k SYMBOL res -288 -80 R0 SYMATTR InstName R5 SYMATTR Value 3k SYMBOL npn 416 -96 R0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL res 464 160 R0 SYMATTR InstName R3 SYMATTR Value 2.2k SYMBOL cap 608 176 R0 SYMATTR InstName C4 SYMATTR Value 10uF SYMBOL res 496 64 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R6 SYMATTR Value 1.5k SYMBOL res 112 240 R0 SYMATTR InstName R7 SYMATTR Value 3k SYMBOL res 224 240 R0 SYMATTR InstName R8 SYMATTR Value 3k SYMBOL Opamps\\TI -80 96 R0 SYMATTR InstName U1 SYMATTR SpiceModel TL072 SYMBOL res 640 64 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 53 VBottom 0 SYMATTR InstName R9 SYMATTR Value 1.5k SYMBOL cap 752 176 R0 SYMATTR InstName C5 SYMATTR Value 10uF TEXT -320 -208 Left 0 ;Phase Shift Oscillator\n(to drive tremolo circuit) TEXT 928 -208 Left 0 ;April 4, 2011 TEXT -328 512 Left 0 !.tran 0 35 0 .00001 TEXT -40 280 Left 0 ;Speed Pots\n(ganged) TEXT -40 400 Left 0 ;1Hz to 10Hz TEXT 952 -168 Left 0 ;VE3WWG TEXT -192 120 Left 0 ;TL072

"Warren"

Ok folks- I figured it out for myself. Now I won't forget the lesson. :)

This arrangement allows you to configure your input impedance, regardless of any voltage divider bias requirement you might otherwise have used.

** The most important info is not supplied in your links - ie where the 60 volts DC comes from. I suspect it comes from the ( unregulated ) supply rail of a power amplifier.

Using a simple divider across the rails of that pre-amp to bias the base of a transistor means the output point will be bouncing up and down like a yo-yo in operation as the 60 volt rail bounces up and down. Be nice of the designer has used a zener to stop that.

The feedback bias arrangement used is largely insensitive to variations in the DC supply rail and also to variations in transistor beta.

.... Phil

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The power supply was provided in the following month's article:

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Yes, the +60 volt supply is unregulated. The only thing there in Fig 5, is some LP filters on the supply line using R1/C1, R21/C15 and R29/C22.

Your assessment makes sense. No wonder the same arrangement was used virtually everywhere in the small signal stages.

Thanks, Warren