Baxandall Class-D Oscillator paper accessible on my web-site

May 25, 2011 29 Replies

Oh, hell no. The above was used for hand-drawn or drafted schematics (even for patents). When doing automated logic drawings (ALDs), even with laser printers, we used this sort of symbol (characters used are pretty accurate):

Bipolar: Resistor: (you have to know (you have to know that that EBQZ is an NPN) CD9D is a 1K resistor)

+----------+ +----------+ | Q | | R | | EBQZ-A-A | | CD9D-A-A | -C | | | | | -| |- | B- | | | | | | -E | | | | | | |

Capacitor Capacitor (polarized) - O R - (polarized) +----------+ +----------+ | C | | R | | ZQIJ-A-A | | ZQIJ-A-B | | | | | -+ |- -| +- | | | | | | | | | | | | | | | |

NAND Gate: Same gate (negative logic) +----------+ +----------+ | && | | OR | | EAAD-A-A | | EAAD-B-A | -| | -& | | | | |- | &-- | | | | | | -| | -& | | | | |

The four character code is the Block Transfer Rule (BTR) that describes the function of that block to the various systems (layout tool, simulator, whatever), the first character after that is the "Block Hardware Code", which shows how the block is used (a sub-type of the BTR, if you will), and the second digit is the Block Representation Code, which describes how it's drawn on the page. Makes schematics *so* easy to read. ;-) Note that the target audience was another computer. ;-)

Intel made a few changes when they got the system to design the Pentium. ;-)

Anyway, you get the idea... ;-)

That's really, really painful! Sheesh!

...and to think that we have debates over whether it's better to draw, e.g., hex inverters as one big package or six discrete ones! (My answer is, "do both -- there are good reasons for wanting one or the other depending on the particular design, it's not like we're going to run out of disk space storing library files, you know?" -- But there are those who believe that, no, there should be One True Symbol for any given part and really dislike the thought...)

---Joel

In PSpice Schematics I have _692_ custom-made symbols ;-)

Not all are components, however. Some are special test function gimmicks, such as the LoopGain function shown on my website. ...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

s

Did you contact Jim Williams and send him a link?

Count me on your side. However, it would be nice to put them all in the same library "symbol" and allow the designer to select the one for that situation. It would also be nice to be able to let the tools (or using back annotation) fill in the pin numbers. There are things, that at least OrCAD, doesn't have to allow this.

Our layout guy (also the librarian) made a cap symbol for every P/N in our system. It works out OK, but it puts a separate part in the cache for each part used. The jury is still out whether I like the approach. It's not going to work for resistors, I don't think (just too many).

I completely agree; ORCAD is rather primitive in how it handles parts libraries. E.g., in Pulsonix, there are footprint libraries, symbol libraries, and parts libraries (all separate file types) -- one part can be joined up to any number of symbols and/or footprints.

Can you use (library part) aliases for that? We were doing that for awhile, although then when we started rolling out a new ERP system it was unclear whether or not the CIS portion or ORCAD would integrate cleaner with aliased parts, so we stopped (...and we've been busy enough that the original question hasn't been resolved yet).

---Joel

hes

of

He's not known for reading his e-mail, and it's not something I'd phone him about - he's not going to rewrite AN-45 once again just to include a reference to Peter Baxandall's paper.

-- Bill Sloman, Nijmegen

Symbols are people viewing, netlists and BOM's can't be anything else you desire. ...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

Gack! Stumble-bum as I wake up :-(

... netlists and BOM's CAN be in any format you desire.

You just need to understand the capabilities of your tools. ...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

Aliases are too dumb, to do much at all, from what I can tell. It's just another name for a part. The problem is pulling in all the part properties from the release system (Agile). I want to try CIS, but we only have one node-locked license that the layout guy uses (useful, huh?).

We've been busy too (I've already done a half dozen boards this year and probably have at least that many in queue), so he stopped at the caps (and there a lot of new ones to go in there). We have to do something about ICs, though. As discussed above, I like several versions of a part (a necessity with FPGAs) and there is no good way to keep them organized.

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