Battery charging with intermittant power source

Did you read the Unitrode AppNote? The regime used by that controller chip (UC3906) can be restarted at will regardless of the SOC of the SLA. The only requirement is that the charger can deliver *enough* current to trigger the changes to the charge mode.

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=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PNP power =A0 =A0 =A0 =A0 =A0 =A0 =A0

------ + 8.3

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b T1 =A0 =A0| =A0 =A0 =A0|

| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0| =A0 = =A0

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0R3 5k9

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0|

=A0 about +2.4 =A0 =A0 c =A0 =A0 =A0 c =A0 =A0 =A0|

-------------- b =A0 =A0 =A0 =A0 =A0 b----|

=A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0e =A0 =A0 =A0 e =A0 =A0 =A0|

=A0 =A0R1 150 | =A0 =A0 =A0 =A0| T2 =A0 =A0| T3 =A0 | =A0

=A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0|_______| =A0 =A0 =A0R4 2k4

--- =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0|

=A0 =A0 =A0 =A0 =A0=3D=3D=3D 10u =A0 =A0 =A0 R2 =A0 =A0 =A0 =A0///

=A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 ///

=A0 =A0 =A0 =A0 /// =A0 =A0 =A0 =A0 2 x NPN =A0

I've done the PNP pass in chips. [It's a common scheme since PNPs can generally handle more voltage than fets on a chip. Very common on switchers that bootstrap their power to the control circuitry.] ] I'd be more inclined to use a Pfet (probably two back to back to get around reverse power). The PNP isn't great for low drop out. You have to add anti-saturation circuitry. The efficiency is poor near saturation since the base current goes up.

I don't trust software. Too many bugs.

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=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PNP power =A0 =A0 =A0 =A0 =A0 =A0 =A0

------ + 8.3

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b T1 =A0 =A0| =A0 =A0 =A0|

| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0| =A0 = =A0

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0R3 5k9

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0|

=A0 about +2.4 =A0 =A0 c =A0 =A0 =A0 c =A0 =A0 =A0|

-------------- b =A0 =A0 =A0 =A0 =A0 b----|

=A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0e =A0 =A0 =A0 e =A0 =A0 =A0|

=A0 =A0R1 150 | =A0 =A0 =A0 =A0| T2 =A0 =A0| T3 =A0 | =A0

=A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0|_______| =A0 =A0 =A0R4 2k4

--- =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0|

=A0 =A0 =A0 =A0 =A0=3D=3D=3D 10u =A0 =A0 =A0 R2 =A0 =A0 =A0 =A0///

=A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 ///

=A0 =A0 =A0 =A0 /// =A0 =A0 =A0 =A0 2 x NPN =A0

There are high current polyswitches. [Raychem for you old timers.]

Here is the PEPI website

I gather the PEPI is a cheaper solution over polyswitch since I never saw a polyswitch in a battery pack. PEPI or similar are common.

On a sunny day (Sun, 11 Jan 2009 22:55:12 -0800 (PST)) it happened " snipped-for-privacy@sushi.com" wrote in :

Well, that will severely limit what you can do. Usually the use of an integrated computer solution like PIC, with software in FLASH can save many many analog and digital components, add amazing features (that cannot easily be done in hardware at low cost or complexity), so improve reliability because of lower component count, etc. Not even mentioning networking and remote features.

Although I am not using that 100% here, the idea of just doing ADC on any value, doing all processing digital, and then, if needed, doing DAC, sort of is nice. In circuit re-programming is nice too. Maybe get rid of all those wires from board modifications... Or even update a program remotely... May save you a long trip.

I did see some negative remarks about doingg it digital, and sure, some things can be done analog, but this digital processing just requires a bit different way of thinking, the nice features come by themselves, and, as those features have very little hardware cost (just code), are a good way to leave the competition behind, especially if you can read protect the FLASH.

In fact I am wondering how much analog is here to stay.... Except perhaps for extreme speeds and precisions, but ADCs get better all the time too. We even have digital radio, and, with FPGAs with serial links in the 8 Gbits/s range 'speed' gets an other dimension. The 75 Baud time is long long gone ;-)

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value,

nice.

d,

he FLASH.

the time too.

its/s range

But I'm an analog guy;-)

Note that digital often is often a higher power solution for many products. Generally a hybrid is the way to go. I'll give you an example of a design screw-up I made by going digital versus analog. It was on a SMB interface circuit. I used the system clock to add some wait states in the design since it was precise and already there. Problem was the clock got shutdown down in powerdown mode, so I had no clock when it was time to wake up the chip with a bus command. Fortunately, there were other mistakes on the chip (a multiperson project), so I wasn't the only person screwing up big time. The 2nd pass used one-shots for the timing.

---------- + 8.3

| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b T1 =A0 =A0| =A0 =A0 =A0|

=A0| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0| = =A0 =A0

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0R3 5k9

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0|

=A0 =A0 about +2.4 =A0 =A0 c =A0 =A0 =A0 c =A0 =A0 =A0|

=A0| =A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0e =A0 =A0 =A0 e =A0 =A0 =A0|

=A0| =A0 =A0R1 150 | =A0 =A0 =A0 =A0| T2 =A0 =A0| T3 =A0 | =A0

=A0| =A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0|_______| =A0 =A0 =A0R4 2k4

=A0|---- =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0|

=A0| =A0 =A0 =A0 =A0 =A0=3D=3D=3D 10u =A0 =A0 =A0 R2 =A0 =A0 =A0 =A0///

=A0R2 150 =A0 =A0 --- tant. =A0 =A0 | 150

=A0| =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 ///

// =A0 =A0 =A0 =A0 /// =A0 =A0 =A0 =A0 2 x NPN =A0

Jfets are often used in bicmos chips. You can make them out of the epi layer. They are great because like you stated, then are on at low voltages.

In a discrete design, in theory you could use depletion mosfets.

On a sunny day (Mon, 12 Jan 2009 13:35:01 -0800 (PST)) it happened " snipped-for-privacy@sushi.com" wrote in :

Yes, and we all make mistakes... This is a case of programmable hardware, new code for an FPGA. One shots, sure... capacitors, resistors... tolerances. I have seen defective caps in delays circuits., remember a SECAM to PAL transcoder, to be used in 15 minutes for Eurovision news... Fixed that one on time, never opened a SECAM decoder before. They had all test points neat on the outside. The French can make nice professional equipment.

------------ + 8.3

=A0 | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b T1 =A0 =A0| =A0 =A0 =A0|

=3D =A0| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0= | =A0 =A0

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0R3 5k9

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 | =A0 =A0 =A0|

| =A0 =A0 about +2.4 =A0 =A0 c =A0 =A0 =A0 c =A0 =A0 =A0|

LM317L-------------- b =A0 =A0 =A0 =A0 =A0 b----|

=A0| =A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0e =A0 =A0 =A0 e =A0 =A0 =A0|

=A0| =A0 =A0R1 150 | =A0 =A0 =A0 =A0| T2 =A0 =A0| T3 =A0 | =A0

=A0| =A0 =A0| =A0 =A0 =A0| =A0 =A0 =A0 =A0|_______| =A0 =A0 =A0R4 2k4

=A0|---- =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0|

=A0| =A0 =A0 =A0 =A0 =A0=3D=3D=3D 10u =A0 =A0 =A0 R2 =A0 =A0 =A0 =A0///

=A0R2 150 =A0 =A0 --- tant. =A0 =A0 | 150

=A0| =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 ///

/// =A0 =A0 =A0 =A0 /// =A0 =A0 =A0 =A0 2 x NPN =A0

Check out the ones from

They make darn good pass elements in low current LDOs.

I just had a great idea for a new product.

Lets package DN2470s in a glass package with a pair of back to back red LEDs and a power resistor. The LEDs and the resistor will make it get hot and glow red. The MOSFET would work ok as an audio amplifier.

On a sunny day (Mon, 12 Jan 2009 13:42:24 -0800 (PST)) it happened " snipped-for-privacy@sushi.com" wrote in :

mm Here is a simple example for a MOSFET low dropout regulation I just composed: ftp://panteltje.com/pub/MOSFET_low_dropout_regulator_with_short_circuit_protection.gif

Output is over R7, so the regulator is in the *minus* lead. Q1 is for start up, to hold current limit inactive for about 1.5 ms (C1 + R8). The current is then measured by using the voltage drop over the MOSFET. If it exceeds .75 V then Q1 starts conducting, and the MOSFET is switched off, resulting in the voltage over it to become much higher, and Q2 conducting more, output goes then to zero permanently. It will, depending on the type of MOSFET, easily do 45A..... before it either evaporates (too big a value for C1, too long current sense inhibit), or melts (huge heatsink needed). You can limit much lower, I use a LM324 in my other project to sense the voltage over the MOSFET, but did not find a spice model for the LM324 for LTspice, so maybe later. C2 is needed to keep if from going bad if entering current limit.

You can leave Q1, Q2, and associated components out, and use a fast fuse I guess.... Good thing is that it seems stable with about any MOSFET I select. Ripple rejection is about 10x for small signals..

On a sunny day (Wed, 14 Jan 2009 16:05:55 GMT) it happened Jan Panteltje wrote in :

ftp://panteltje.com/pub/MOSFET_low_dropout_regulator_with_short_circuit_protection.gif

evaporates

heatsink needed).

voltage over the MOSFET,

guess....

Here is the same one with >25A trip. The trip value is set by R10. It pre-biases Q1, so it opens earlier, at a lower volatge across the MOSFET. Had to increase C2 to 220pF to avoid oscillations in the trip region.

On a sunny day (Wed, 14 Jan 2009 16:05:55 GMT) it happened Jan Panteltje wrote in :

ftp://panteltje.com/pub/MOSFET_low_dropout_regulator_with_short_circuit_protection.gif

evaporates

heatsink needed).

voltage over the MOSFET,

guess....

Here is the same one with >25A trip. The trip value is set by R10. It pre-biases Q1, so it opens earlier, at a lower volatge across the MOSFET. Had to increase C2 to 220pF to avoid oscillations in the trip region. Forgot the link: ftp://panteltje.com/pub/MOSFET_low_dropout_regulator_with_short_circuit_protection2.gif

sed:

..

R8).

off,

more,

ther evaporates

heatsink needed).

voltage over the MOSFET,

I guess....

I would use a controller chip over discretes. For one thing, the long tail pair matching in the error amp will be better over discretes.

On a sunny day (Wed, 14 Jan 2009 14:08:41 -0800 (PST)) it happened " snipped-for-privacy@sushi.com" wrote in :

That is absolutely true. However we should never forget what we use it for, and high accuracy is not really a big thing here. What counts is that I have the transistors laying about :-) I am actually working on something like this, as a ripple filter stage coming after a switch mode computer supply for 25A or so. The idea is to do AC peak detection on the _output_, and then use that detected voltage to create a voltage drop (low) over the series regulator, so that drop is just enough to filter out the ripple. Dunno if that ever has been done, you cannot go for 'zero ripple', but set for example for 1 mV or so. Computer switchmodes are really really noisy, and this way you minimise losses, so for 1V ripple drop the 12V PC supply to about 11V ripple free. Will try some simulation tomorrow perhaps, and yes, that uses a LM324 opamp, not a long tailed pair.

e.

mp,

The nice thing about controller chips is a thousand customers have flogged the design by the time you get to use it. There are always gotchas that one person may not consider in the design until a customer does something you as the designer didn't anticipate. There are always design elements in a chip that you don't reveal in the datasheet. As a chip designer, I am always hesitant to roll my own for stuff I build for myself. There is a lot of screw up derived knowledge in every chip.

LDOs are funny things. Too much gain can be a problem. Generally a single gain stage works best since you have to deal with pole shifting due to the external load. So beware of using multistage op amps in such circuits.

Wouldn't you just pick a voltage and linear regulate to it? The trouble with your sensing scheme is it will need to take into account spikes on the supply due to load variations. While you are thinking of a feedforward design, there is feedback from the load variance to consider.

Yeah, but don't you think that about 900 of them probably just used the exact example circuit shown on the first page of the data sheet? :-)

What kind of ICs do you design, Miso?

---Joel

On a sunny day (Wed, 14 Jan 2009 18:41:08 -0800 (PST)) it happened " snipped-for-privacy@sushi.com" wrote in :

Yes

No, I am not talking about a feed forward design.

I did mean this: 10mV reference | noisy DC source -- series regulator --- negative peak detector - level comparator ---- | | | |

------------------------

reference

comparator ----

------------------------

anyways.

OK, it works in LTspice, with a generic opamp (whatever that may be :-) ):

Here is with 2 volt sine ripple superimposed on 12V battery, see how it finds the optimum setting: ftp://panteltje.com/pub/two_volt_ripple.gif The red line is the battery + ripple. The green line is the output voltage The cyan line is the output of opamp U2. That will go chaotic, just fine, ripple noise is chaotic too ;-) The chaos is filtered out in the loop filter.

Here is with half a volt ripple: ftp://panteltje.com/pub/half_volt_ripple.gif

And here with almost none (50 mV) ripple: ftp://panteltje.com/pub/50_millivolt_ripple.gif

See how close we get with the low dropout to the 12V battery voltage in this case! As I did set a maximum ripple with R15 / R16 (presented to comparator U2), the loop now longer is active, so 50 mV is allowed, and the MOSFET is 100% on. Or almost 100% anyways. Dunno if I will ever build this, more a proof of concept. Minimum dissipation in a linear series regulator.

Note that I disabled the short circuit protection by shorting the collector of Q1 against it's emitter. Measuring the drop over the MOSFET will not work here, those components should be removed.