bandpass filter

Ah, okay.

I have, I confess, been guilty of a terminological inexactitude.

I ought to have remembered from the phase velocity/group velocity distinction that the group delay equals the envelope delay only in the limit of slowly varying envelopes. The same is true of group delay in circuits.

Sharp resonances can show group velocities greater than c, without energy or information being transferred superluminally, and similarly sharp filters can have negative group delay without needing a time machine.

Mea culpa, mea culpa, mea maxima culpa. Thanks for the gentle correction!

Cheers

Phil Hobbs

No "normal" one.

This is very interesting.

s with

ay

You're missing some essential features:

1. In the patent, the "second" resonator has a resistor in series with it; it is critical
2. Feedback was important for the patented circuit. Opening the loop on t he patented circuit "destroys" the effect you're looking for.
3. The patent circuit resonators are identical. You stagger tuned yours. You shouldn't have to stagger if you get it right.

Now the feedback did seem to "couple" the resonators in the sense of produc ing the double humped amplitude response. What is unclear for an all passi ve circuit is how they can be coupled and still provide the "second" resona tor having a resistor in series with it. There may be some way of tapping, but it isn't obvious to me (yet).

The printing is poor. I can't be sure of all the equations -- the denomina tor is missing in (7) for example. I would have to go through it in detail and see if there is a gain-less form of those equations that can be synthe sized into a network.

By the way, the patent doc really doesn't express the "magic" in english.

OMG- don't tell me someone needs to hold your hand on this one too!

On Wednesday, August 7, 2013 10:07:42 AM UTC-7, Phil Hobbs wrote:

yep.

.)

re: "an LCR all-pass filter is always a lattice"

========================= ======= .asc

-------------------------------- Version 4 SHEET 1 6120 3588 WIRE -240 -672 -320 -672 WIRE 1152 -672 -240 -672 WIRE 1264 -672 1152 -672 WIRE 1472 -672 1344 -672 WIRE 3056 -672 1472 -672 WIRE 3104 -672 3056 -672 WIRE 1152 -592 1152 -672 WIRE 1184 -592 1152 -592 WIRE 1312 -592 1248 -592 WIRE 1376 -592 1312 -592 WIRE 1472 -592 1472 -672 WIRE 1472 -592 1440 -592 WIRE -240 -528 -240 -672 WIRE 3056 -512 3056 -672 WIRE 1312 -496 1312 -592 WIRE 1312 -400 1312 -432 WIRE -240 -288 -240 -448 WIRE 1312 -288 1312 -320 WIRE 1312 -288 -240 -288 WIRE 3056 -288 3056 -432 WIRE 3056 -288 1312 -288 WIRE -240 -240 -240 -288 FLAG -240 -240 0 FLAG 3104 -672 OUT_00 IOPIN 3104 -672 Out FLAG -320 -672 IN_00 IOPIN -320 -672 In SYMBOL res 3040 -528 R0 SYMATTR InstName R_load00 SYMATTR Value {Rload00} SYMBOL voltage -240 -544 R0 WINDOW 0 25 23 Left 2 WINDOW 3 25 93 Left 2 WINDOW 123 36 64 Left 2 WINDOW 39 27 106 Left 2 SYMATTR InstName Vsrc00 SYMATTR Value "" SYMATTR Value2 AC 2 SYMATTR SpiceLine Rser={Rsrc00} SYMBOL ind 1248 -656 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value {La} SYMATTR SpiceLine Rser=1e-12 SYMBOL cap 1440 -608 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value {Ca} SYMATTR SpiceLine Rpar=1e12 SYMBOL cap 1248 -608 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value {Ca} SYMATTR SpiceLine Rpar=1e12 SYMBOL ind 1296 -416 R0 SYMATTR InstName L4 SYMATTR Value {Lb} SYMATTR SpiceLine Rser=1e-12 SYMBOL cap 1296 -496 R0 SYMATTR InstName C4 SYMATTR Value {Cb} SYMATTR SpiceLine Rpar=1e12 TEXT -200 -976 Left 2 !.ac oct 100 .1 10 TEXT -1312 -2784 Left 2 ;o TEXT 5416 1528 Left 2 ;o TEXT -384 -1080 Left 2 !.net I(R_load00) Vsrc00 ; Rsrc & R_load determined from Vsrc and R_load TEXT -200 -864 Left 2 !.SAVE S11(vsrc00) S21(vsrc00) S12(vsrc00) S22(vsrc00 ) TEXT -352 -1192 Left 2 !.param Rsrc00 = 1 TEXT -360 -1152 Left 2 !.param Rload00 = 1 TEXT 1632 -1040 Left 2 !.param La = 2*Rsrc00/(wr*Q) TEXT 1632 -1160 Left 2 !.param wr = 2*pi TEXT 1632 -1104 Left 2 !.param Q = sqrt(2) TEXT 1640 -904 Left 2 !.param Lb = Rsrc00*Q/(2*wr) TEXT 1656 -984 Left 2 !.param Ca = Q/(wr*Rsrc00) TEXT 1632 -840 Left 2 !.param Cb = 2*Q/(wr*(Q*Q - 1)*Rsrc00)

========================= ======= .plt

-------------------------------- [AC Analysis] { Npanes: 1 { traces: 1 {536870914,0,"S21(vsrc00)"} X: (' ',0,0.1,0,10) Y[0]: ('µ',0,0.999986184584876,2e-005,1.00001381560599) Y[1]: (' ',0,-360,30,0) Log: 1 2 0 GridStyle: 1 PltMag: 1 PltPhi: 1 0 } }

On Wednesday, August 7, 2013 10:07:42 AM UTC-7, Phil Hobbs wrote:

yep.

.)

re: "an LCR all-pass filter is always a lattice"

========================= ======= .asc

-------------------------------- Version 4 SHEET 1 6120 3588 WIRE -240 -672 -320 -672 WIRE 1152 -672 -240 -672 WIRE 1264 -672 1152 -672 WIRE 1472 -672 1344 -672 WIRE 3056 -672 1472 -672 WIRE 3104 -672 3056 -672 WIRE 1152 -592 1152 -672 WIRE 1184 -592 1152 -592 WIRE 1312 -592 1248 -592 WIRE 1376 -592 1312 -592 WIRE 1472 -592 1472 -672 WIRE 1472 -592 1440 -592 WIRE -240 -528 -240 -672 WIRE 3056 -512 3056 -672 WIRE 1312 -496 1312 -592 WIRE 1312 -400 1312 -432 WIRE -240 -288 -240 -448 WIRE 1312 -288 1312 -320 WIRE 1312 -288 -240 -288 WIRE 3056 -288 3056 -432 WIRE 3056 -288 1312 -288 WIRE -240 -240 -240 -288 FLAG -240 -240 0 FLAG 3104 -672 OUT_00 IOPIN 3104 -672 Out FLAG -320 -672 IN_00 IOPIN -320 -672 In SYMBOL res 3040 -528 R0 SYMATTR InstName R_load00 SYMATTR Value {Rload00} SYMBOL voltage -240 -544 R0 WINDOW 0 25 23 Left 2 WINDOW 3 25 93 Left 2 WINDOW 123 36 64 Left 2 WINDOW 39 27 106 Left 2 SYMATTR InstName Vsrc00 SYMATTR Value "" SYMATTR Value2 AC 2 SYMATTR SpiceLine Rser={Rsrc00} SYMBOL ind 1248 -656 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value {La} SYMATTR SpiceLine Rser=1e-12 SYMBOL cap 1440 -608 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value {Ca} SYMATTR SpiceLine Rpar=1e12 SYMBOL cap 1248 -608 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value {Ca} SYMATTR SpiceLine Rpar=1e12 SYMBOL ind 1296 -416 R0 SYMATTR InstName L4 SYMATTR Value {Lb} SYMATTR SpiceLine Rser=1e-12 SYMBOL cap 1296 -496 R0 SYMATTR InstName C4 SYMATTR Value {Cb} SYMATTR SpiceLine Rpar=1e12 TEXT -200 -976 Left 2 !.ac oct 100 .1 10 TEXT -1312 -2784 Left 2 ;o TEXT 5416 1528 Left 2 ;o TEXT -384 -1080 Left 2 !.net I(R_load00) Vsrc00 ; Rsrc & R_load determined from Vsrc and R_load TEXT -200 -864 Left 2 !.SAVE S11(vsrc00) S21(vsrc00) S12(vsrc00) S22(vsrc00 ) TEXT -352 -1192 Left 2 !.param Rsrc00 = 1 TEXT -360 -1152 Left 2 !.param Rload00 = 1 TEXT 1632 -1040 Left 2 !.param La = 2*Rsrc00/(wr*Q) TEXT 1632 -1160 Left 2 !.param wr = 2*pi TEXT 1632 -1104 Left 2 !.param Q = sqrt(2) TEXT 1640 -904 Left 2 !.param Lb = Rsrc00*Q/(2*wr) TEXT 1656 -984 Left 2 !.param Ca = Q/(wr*Rsrc00) TEXT 1632 -840 Left 2 !.param Cb = 2*Q/(wr*(Q*Q - 1)*Rsrc00)

========================= ======= .plt

-------------------------------- [AC Analysis] { Npanes: 1 { traces: 1 {536870914,0,"S21(vsrc00)"} X: (' ',0,0.1,0,10) Y[0]: ('µ',0,0.999986184584876,2e-005,1.00001381560599) Y[1]: (' ',0,-360,30,0) Log: 1 2 0 GridStyle: 1 PltMag: 1 PltPhi: 1 0 } }

I was a little hesitant to post this circuit, lest I be seen to be dumping on anyone. If it makes anyone feel better, I have no idea how it works.

I started with the idea of summing the output of two peaky tanks, ie narrow bandpass filters, at slightly different frequencies. The sweep generator would feed each tank through a delay line, and the delays could be adjusted to arbitrarily set the phase of each of the two peaks. Seemed to me that I could slam the summed-output phase all over the place midband with no thermodynamics crisies.

I did that and it turned out it didn't need the delay lines, so I ripped them out. This is a weird variant on the usual ladder-type top-coupled bandpass filter.

The extra bonus is that the midband phase shift is zero, and the nearby slope is adjustable.

Can you be more specific? Do you have a circuit? One different from the one I posted?

This is fun stuff.

Another interesting example:

and the plotfile:

(It has a 30000 character long line in it for a PWL source.)

The positive phase slope at low frequencies makes this bandpass filter look like its output is preceding its input, but it isn't really--the input is actually there the whole time.

Cheers

Phil Hobbs

Okay, lattice or bridged-T, or equivalents, quite right. Wye-delta and all that.

Cheers

Phil Hobbs

That's not MHz, it's mHz. Note that the caps are 1 farad and the inductors are 1 Henry... not typical VHF values.

It's normalized for simulation, as filters often are.

If you're going to be snarky, try to be right.

Don't forget the variance in copper dimensions themselves due to etch.

How bad would it be to put two shunts on the PCB, one being like a test pattern. For each batch of board, You measure the "test pattern shunt" and derive a calibration factor for each batch of boarda.

In semiconductors, there are two philosophies in critical dimensions. The names vary. One philosophy is you set up the flow so that the dimension drawn is the same as the dimension on the chip. The other is you set up the process so the minimum dimensions are the most repeatable and as small as possible. Spice has parameters to adjust the expect dimensions versus drawn dimensions.

I assume PCB manufacturing is similar. They probably set up the process to make reliable fine pitch traces, but perhaps to the detriment of the dimensional accuracy of larger structures. So there may be some magic dimension where the trace dimensions are most accurate.

Another trick often used in semi is to put dummy elements in the layout. That is, for the strip of PCB that is your shunt, you place a dummy trace on each side of the strip, just floating. The idea is the etch rate may depend on the spacing to the next trace.

PCB trace resistances are not very repeatable, 10% if you're lucky, and the TC is about 0.4% per degree C.

Just build in a switchable load, like a current sink or even just a resistor switched to ground, and continuously calibrate the test trace. That will take out initial etch variations and the horrible TC of copper.

The current could be a small fracton of the load current, applied at a low duty cycle. Do some signal averaging.

Or just buy a low-ohm 1% shunt resistor.

Or you can investigate what I suggested. Knowing the process in better detail can yield products you thought were not feasible. Have you tried dummy devices?

I had to do a ECL board once for testing a competitors device. You would be amazed what can be accomplished if you actually work with the board vendor to understand their CDs (critical dimensions). OK, I was making a few board and used a local vendor, paying top dollar. Slopping the shit out in China may be different, so you might not have the same quality.

These are good suggestions. I need to consider them in detail. Thanks again for your help.

I often add test traces to PC boards to measure impedance with TDR, and trace resistances with a 4-wire measurement. If you put reasonable toleances on the fab drawing and the usual words like "1 oz copper" and don't specify trace impedances, you'll get 50 ohm traces that might be 43 or 55. Trace resistances seem to always come out high, because plating copper is expensive. If you ask for 1 oz, they start with 1/2 or 1/4 and plate up to somewhat under 1. The couple of times I called out a minimum ohms/square, the board house got confused. Shunt resistors would probably be cheaper than buying resistance-controlled boards.

I've said START WITH 2 OZ COPPER, which works, but you might get 2.2 and you might get 2.8 finished.

Lots of people call out trace impedances and tolerances, and boare houses handle that somehow. But that runs the cost up.

You could parallel a few 2-cent low value resistors to make a shunt.

Nope. Neither will a BP at the clock fundamental.

A PLL IS a BP, as in...

(First posted here, October, 2012)

Observe the ThetaV/ThetaR equation near the bottom of Page 1.

The neat thing about an Analog PD PLL is you can directly drive it with a noisy square wave and the output will be a clean square wave.

And, for fixed clock retrieval, you can make the loop filter _very_ narrow, making for an equivalent Q much greater than 50, yet track dead-on the clock frequency. ...Jim Thompson

Suggestion for people who have PCBs fabricated to their drawings:

Measure some trace resistances on various boards, in uohms/square. Report them here, alongside whatever fab instructions you provided.

US versus offshore fabricator results would be interesting, too. I'm sure some low bidders must skimp on plating.

No.

The allpass has a phase shift too. In fact that is the very reason it exists. So, "no, you don't want that."

I am working on something, but not "allpass."

There is no such thing as "baseband" or "bandpass" allpass. That is because it is *all* pass, with much emphasis on the word "all."

The question on all-pass is merely where the shift is and the Q.

Okay, but be careful of that as a general assumption. Any AM to PM in your system can wreck your day.