Attainable PWM accuracy?

Thanks, that's a nice part, and about the same price. It needs a bunch of extra pins though, and they're a very scarce resource ATM.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

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it does I2C that is only 2 pins

Win,

Neat idea but it doesn't seem to work effectively for other than 50% duty cycle. In my simulation it is worse than a simple filter for duty cycles such as 10%.

kw

Would it do any good to sum two PWMs that are out of phase? One more uP pin, one more resistor.

Sort of like this:

tirsdag den 15. oktober 2019 kl. 19.34.21 UTC+2 skrev John Larkin:

I dunno what Keith did but Woodward's trick works great for me. I've meant to post it for years. He sums an equal but out-of-phase error current into the filtering node. That reduces the ripple current ~a couple orders of magnitude *before* it gets to the filter cap.

See piglet's post for the whole enchilada.

After filtering, switch resistance is the next DNL limitation. A high-precision application will need a switch resistance cancellation scheme.

The last frontier is delta Tpd in the switches.

Cheers, James

Turned out we needed two DACs, so I bailed on the PWM+reference and picked a dual 12-bit LTC2633, which was cheaper than just the REF5030. We're using an I2C EEPROM anyway, so it didn't cost any pins, as you say--it's just that I2C has nasty lockup states, so we were a bit reluctant to put any more stuff there.

I used the previous PWM pin to run a PNP to allow turning off the I2C power just in case, so both the hardware and software humans are happy.

AIUI SMBus is basically I2C with the lockup states fixed--I wonder why it's apparently still uncommon except in ambient light sensors.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

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I think most things on pc motherboards are SMBus

I guess the 35ms timeout on SMBus could be an issue for bit banging and SMBus is max 100kHz

piglet, that's an elegant scheme. I'm sitting here struggling to see exactly what R1 is doing. I guess I'll have to write down some equations with the output impedance of the inverters driving the V1 node included. (thanks for sharing.)

George H.

Hi George, yes R1 compensates for the non-zero output impedance of the HC04 (three paralleled) switches. Working back from woodward's description it seems he takes the HC04 Ron per output to be about

40ohms. I guess more modern devices have lower Ron but having R1=R6 elegantly cancels the error.

piglet

OK. Sorry a 'brain cramp' in my analysis... sometimes I make things more complicated than needed. The next order term in the 'error' is of order R2/R6, 1/255

Say referring now to Win's chapter 4x.25 for the ripple cancellation. You obvious need R1=R2, but since C2 is mostly just a DC block cap. Making it a bit bigger than C1 seems like it might be a good idea. Comments? (say ~three times bigger for 8 bits)

George H.

Woodward seems to hint, but doesn't outright claim, that R1 cancels switch resistance error from the low-dac's 1M load. But I've never been able to prove to myself that it compensates that, or corrects the high-dac's switch-resistance error.

(ISTM the real answer is that r3=200k means the main dac switch can tolerate roughly three ohms of switch mismatch before experiencing an lsb error at certain codes.)

As to Phil's original question, doing some calculations, and reviewing this old thread, "SMD TC? 4/8/2012", I think the answer is that about

14 bits seems pretty doable with a single PWM DAC. Beyond that needs splitting the DAC into high and low sections.

Beyond that the more bits, the more filtering, timing accuracy, output impedance, and filtering start biting pretty hard.

The redoubtable Woodward has addressed these in the following link by splitting a 32-bit DAC and filtering with a s/h, all doable with a single analog switch pack and a dual op-amp...

Cheers, James Arthur

Hi James, glad I can help. I started with all these involved equations. (goes for a page or two with much head scratching..) And then I did two simple cases. One with +Vs on MSBs and LSBs grounded and then visa versa.* Then it's a simple voltage divider. In both there is an error that goes as Vs*(1-Ro/R6) where Ro is output resistance. (Assuming R6>>R2>>Ro)

George H.

*With both at +Vs or gnd there is no error.

Oops the 'error' is only the -Vs*Ro/R6 part.

I didn't know about Stephen Woodward. Has he written any books? Other good articles?

GH

Sorry the above is not quite right... I'll think some more... There is this 'uncertainty' caused by R3 (200k) and the output voltage.

GH

OK So the above works when the output voltage is at the 'average' value and on average no current is flowing through R3.

George H.

No books that I know of. Stephen Woodward has contributed many Ideas-for-Design to EDN/ED since at least the early 1990s. I always remember the devastatingly clever things he'd do with PWM'd 4053 analog switches. Reminds me of the clever tricks Jim Thompson would do with a TL431 :)

piglet

Thanks piglet, I found several EDN articles. What's sad is that there are no pictures /schematics to go along with the older ones.

I read an article on diode laser thermal control that I found a little confusing... maybe I should send him an email? Here,

Did he ever post here?

George H.

My guess is he'd be happy to respond to an email.

Not that I recall.

--
 Thanks, 
    - Win