ts
I think that metastabillity is a bit over rated as a problem with current FPGA technology. As it was explained by the experts at Xilinx, the gain/bandwidth of the FFs is high enough that only a small number of ns is required to resolved metastability. So it will often be minimized auto-magically by your default design. Of course there are things you can do to mess it up and that is what you need to know, how not to cause metastability. Avoiding it is easy.
eThere are some, but I haven't see you make any mistakes other than the slow rise/fall time input. That is actually not FPGA related and can mess up any logic that you design with.
Books are written about the theoretical aspects of design (at least text books seem to be) and timing constraints are not very much "theoretical". In fact, they are hard to put in a text book because they are an issue of the vendor and subject to modification at their whim, not that this happens much. On the other hand, the vendors have tons of docs on timing constraints and many, many other topics of FPGA design. The vendors have a vested interest in your success. Sometimes they act this way.
,Often the happy middle depends on the project goals and the urgency of the fix. I actually got a design note published based on using a Zener diode to drop a 5 volt signal to a 3.3 volt FPGA input! At the time it seemed like an obvious thing and greatly simplified an otherwise messy fix.
Rick