I have had two 2N7002 broken for no apparent reason. I used them for shifting logic levels, and thought that they are not very critical (until they stopped working that is). I used 100n capacitors as shields in drain and gate.
I thought that with 2N700x you just put them in place and forgot them. Now it seems i have to use some really large power fet. Static should not kill those.
I've always found them to be very reliable and rugged.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Depends which kind. There's the 2N7002E, recently discontinued, which has no gate protection. It's great for all sorts of hi-Z tricks such as JL's oscillating light switch, but is a bit delicate for the usual sorts of sub-watt MOSFET jobs.
What did you do with yours?
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Mine is from NXP
There is no mention of ESD or protection. Someone called mosfets without gate protection as three legged fuses. Hopefully there are some protection.
A 3.3V cpu feeds gate via 220 ohm resistance and drain is connected
12V via 10k and to a slip ring input. Both gate and drain have 100n to ground, simplest esd protection i could think.I am beginning to think that those fets are somewhat esd sensitive, and they were initially broken during assembly.
Leif M
The person who does the programming for the cpu just rang and said it was a sw problem. Probably forgot to inilitialize the io port because the processor is new to him. But I am relieved no matter what the bug was.
Well, Leif reports they were OK after all, but yes, these small MOSFETs do need to be treated as static-sensitive items. In the days gone by we'd get MOSFETs in metal cans, with a wire wrapped around them, which we'd remove after assembly, remember that?
--
Thanks,
- Win
They're ESD sensitive, all right. AFAIK all small-to-medium size MOSFETs are, gate protection or no gate protection.
I have some old metal can FETs (3N163) that came with tiny brass springs wound round their leads to make them safer to handle.
There's an old rule, one of JL's faves, that says never to connect a wire from off the board directly to silicon. (Things like voltage regulators and big power transistors are obviously exceptions.) So a bit of resistance and a couple of diodes on the wire to the slip ring would probably increase robustness.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Another exception would be a TVS :)
-- John Devereux
Well, I'd probably want a polyfuse in front of it, but that's because I'm a chicken.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I don't mind board-board connections inside a box, but I avoid wires that connect silicon to the outside world, when I can.
I tested a few various mosfets, 2N7000s and some bigger stuff, with an HV power supply and blown out the gates. Most die at around 70 volts.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reminds me of a class I took where they started out by defining what a "correctly" working computer was. On the list of requirements was that no instruction be capable of causing unrepairable damage. I asked if that implied that repairable damage was ok?
Why does poor initialization of the I/O port cause the FETs to blow up?
-- Rick
Well, it does not but when the computer is inaccessible like ours, it may look like a blown fet.
I may sometimes accidentally believe what I am told.
What happened was something like this: We have had two blown fets. First was when the machine was on my desk. I have seen these kind of problems, made some of my self too. So I must have checked the io pin. Changed the fet and thought those fets are bad. And forgot the whole thing. (I added the capacitors for esd protection though)
When the fet broke second time, the computer was inaccessible. But now the problem was in the sw.
I wonder what really was the problem first time.
I'm not totally clear on this. When the first FET appeared blown, had you reset the computer before making that determination? Cycled power? If the problem survived cycling power that is a pretty impressive feat if the FET wasn't blown. BTW, do the input ESD caps have resistors bypassing them? If not, how does an input charge leak off? I guess when it is connected to a signal that is not an issue, but neither is ESD really.
Just out of curiosity, why use a FET for level shifting rather than a BJT? Are you stepping the voltage range up or down? Does the input swing to ground?
I just came up with a circuit that would shift an input 5V to 3V swing to a 0V to 3V swing without any chance of going (much) above the 3.3 volt rail for the MCU. I used a PNP with an emitter resistor about half the value of the collector resistor with the 5 volt rail as the common point. As the input drops toward 3 volts the output rises to 3 volts. If the input drops below 3 volts which might make the output rise above
3.5 volts, the emitter leg drops below 3.5 volts saturating the BJT limiting the voltage on the output. To make the input robust to voltages above the 5 volt rail I could add a diode while the BJT already conducts for inputs below ground. This is a hard circuit to do damage to.-- Rick
Hi Phil, sure for power inputs but overkill for general I/O's I think.
-- John Devereux
If FET's gates are accessible on PCB/System boundaries, it's better to provide efficient ESD protection, a capacitor Gate-Source has never been a role for protection against ESD aggressions ... and will not be in the future.
H.
Why not? If a human body is 100 pF, and you put a 100 nF cap across the gate, ESD is divided by 1000:1. 10 KV becomes 10 volts.
Many repeated zaps could accumulate voltage, which is why some resistance to ground is a good idea, too.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Ah, I see. I never use TVSes like that, except occasionally the Littelfuse (formerly Harris) SP720.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Don't know about the hypothetic 100nF G-S capacitor behavior on IEC
61000-4-2 tests (With A discharge surge gun) and i did not want to know more aboout it ;-) And i'm not speaking about PCB implementation ... 2n7002 Vpeak GS = 30V or something ...I'm not a physicist, i use a efficient IEC 61000-4-2 protection (NXP) and it is very efficient to get things working with proper PCB implementation :-)
Habib.
On our wall-wart or USB powered boxes, we generally have a polyfuse and a unipolar TVS and a couple big ceramic caps.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
I am not 100% sure because it seemed to be random error and I just forgot it, but usually it is best to check with suitable test sw if there is some gate signal on the gate. If gate swings from 0-3.3V and drain voltage does not change, it is a sign of hw problem.
They should be have but now there "should be" always be an output to drive them.
Input is 0 or 3.3V. Fet gates take only dynamic current.
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