I'm slowly working my way through AoE 3, lots of excellent stuff so far, and came across 3.6.3, running power MOSFETs in parallel in linear mode. I know this has been discussed here in the past and the consensus was that it can't be safely done with regular vertical MOS devices without ballast resistors or some form of active current sharing.
Fig 3.117B looks like a neat trick, which I may have a use for soon. I pulled up the schematic for the HP bench supply mentioned, to see what they used for the diff amp current sink - turns out it's just a 100K resistor to -12V, that's clearly adequate for the job.
What puzzled me is that in the HP schematic, the NPN devices Q4 and Q5 are connected upside down (c & e reversed), the AoE schematic shows them the right way up. Any ideas why HP did this? I'm assuming it's deliberate.
I have seen BJTs connected this way before to get lower saturation voltage, but there doesn't seem to be any advantage to doing it here. Or am I missing something?