annular ring issue

Donut in some layers and pancake in others. If the customer order a donut, don't serve pancake and take a bite in the middle.

We made our own boards. Etched them in the bathroom.

tirsdag den 9. november 2021 kl. 15.06.28 UTC+1 skrev legg:

Well, perhaps I'm out of date. Of the first 24 PCB mfring links in my portable's bookmarks, only two were still in business. No annular ring references on their site. Ditto with such vendors as JLCPCB.

Googling 'removing non-functional pads on inner layers' got me group discussions or software vendors (on a single html page), neither of which are very reliable sources for hard-nosed info on pcb fab.

Would probably have had better luck in Mandarin or Cantonese. . . Perhaps you could supply links to the info you found so easily. Not sure I'd add them to my bookmarks, but they would serve better than dead links.

I have a 30+years library in paper and electronic format that I'd usually consult, but can't reach before Thursday PM. In real designs, putting signal traces through power connectors, or vice versa, is just a symptom of bad planning.

RL

tirsdag den 9. november 2021 kl. 21.44.35 UTC+1 skrev legg:

It appears that all of these manufacturers anticipate board quantities to be too small to justify set-up charges and dedicated production runs. . . .similar to JLCPCB or DKRed.

Board designs for volume mfring are normally panellized, with tooling holes and features specific to the end assembly and test environment, NOT for the convenience of pcb fab. A PCB fabricator mods gerbers at their own risk. . . .

RL

"Lasse Langwadt Christensen" snipped-for-privacy@fonz.dk schrieb im Newsbeitrag news: snipped-for-privacy@googlegroups.com...

But removing the pads usually does not give you more copper for the plane; the area of the annular ring on inner layers is also needed for drill "wander" and positional tolerances (unless your inner pads were large to begin with)

Chris

onsdag den 10. november 2021 kl. 13.56.33 UTC+1 skrev Chris B:

you don't get any extra space if you remove them in postprocessing, but you might if you design for it

I want some software that will predict sheet resistance (electrical or thermal, they are equivalent) for simple arbitrary shapes.

Does anybody have suggestions? I could write one, but the graphical entry is the hard part. ATLC uses a bitmap from Paint, which I guess I could figure out.

When I was in school, some time ago, we cut teledeltos paper, conductive stuff, and measured it.

This is one I use occasionally:

Similar idea to ATLC2, input is a bitmap. I had a similar design, multiple high-current connector pins coming onto a board, it helped a lot with optimising the layout.

Writing bumpfiles is super easy. There's little reason to write anything else, actually--Image Magick will convert them to whatever format you want.

Cheers

Phil Hobbs

"Lasse Langwadt Christensen" snipped-for-privacy@fonz.dk schrieb im Newsbeitrag news: snipped-for-privacy@googlegroups.com...

Even when you design for it, it doesn't give you more room. Top/bottom pads are for soldering, inner pads are for tolerance only. Drilling has e.g.

Chris

That looks cool. The screen shots are silly; they don't show what results look like.

ATLC makes beautiful field plots.

Still, the sheet resistance thing keeps coming up. I'll try CPCA.

Exactly. As you say, if they weren't oversized then what I'll call the breakout rule won't allow the GND copper to fill in anyway.