I am attempting to design a DC-DC step-up converter with a LM3478/88, and I have two issues:
1) Evaluating the V_cs (to set the inductor current limiting R_sen). The V_cs is V_sense - D*V_sl; I have D=0.9; for V_sense and V_sl the datasheet gives *wide* limits, over the voltage and temperature range:
Watch out that you don't fall into the RHP zero trap (continuous mode, >50% duty cycle). Read page 10 again if you think that might be happening.
I was never very fond of WebBench. It always came back with "cannot be done" or whatever which in all those cases was, to say it politely, baloney. Just build it. When I used the LM3478 for the first time it fired up right away and did what I wanted it to do (in that case a pretty extreme Vin/Vout ration of more than 10). For me the only gripe with it and why I didn't use it often is it's highish price tag.
That worst case corresponds to: V_sense = 135mV (minimum) and V_sl =
132mv (maximum) => V_cs=135-0.9*132=16.2
I don't think this is the reason (although the Bode plot on the Webench goes totally crazy with those increased L...), but I have also tried with *decreased* L (and the V_in at the low limit) - it produces the same phenomenon - the L current grows up to the short-circuit current limit, it looks like the chip totally ignores the normal current limit (the Bode plot is ok).
I have V_in min=3.1V, max=6V, v_out=30V, I_out=0.35A, and I could not find a cheaper part.
Indeed, it looks like I'll have to build a prototype to solve the point 2), but what about the 1)?
Looking at the functional block diagram (page 9), I've got an idea: what if the output is in undervoltage condition (that the webench plots suggest)? The output of EA might then swamp the input from the slope compensation, and the PWM comparator would not get triggered at all; the switch reset would happen on the "short-circuit" condition only. But what is V_sense actually, then?
Absolutamente. IMHO WebBench isn't particularly useful, at least not for me. Calculate it by hand and build one. This is no thwack in National's direction, I have just never found these fancy "automatic design" scripts and gizmos to be very useful, regardless of the manufacturer.
As to 1): What is V_sl? And where does that formula and the factor 0.9 come from?
Where do you see V_sense? This chip has two major controls: FB which is typically used to set the output voltage (although I've used it for all kinds of other things). I_sen which limits the max current through the inductor.
So, as long as the voltage hasn't reached the target where FB would be at 1.26V this chip will run "full bore". Same if you design it so it could never get there (wrong inductor value etc.). IOW it will keep "scooping" the max amount of energy on every cycle, going to the current limit on the inductor every single time.
That has always bothered me with this device. I do not allow inductors to get too close to saturation and also don't want to oversize the core for cost reasons. It is better to measure the actual output current and throttle back via the FB input. That is what I did. Detecting a short via the current sense pin is IMHO quite scary so I didn't do it.
Ok, that's a whole 'nother ballgame. I stayed clear of any CCM. You'll have to contend with RHP zero loop compensation and all that nasty stuff. If that goes wrong National had (probably still has) a forum on their site. Their app engineers respond quite quickly there. Or you could contact Fred Embuscado at National, he knows this stuff very well.