Hello
This is from the datasheet, and I don't really understand it:
"Icc quiescent supply current 80uA. deltaIcc additional quiescent supply current per input pin Vi=Vcc - 2.1V, other inputs at Vcc or GND. Vcc=4.5 to 5.5V An or Bn inputs 180uA OE input 675uA DIR input 405uA"
I get the bit about Icc at 80uA, and I get the bit (not quoted) about dynamic power. But what's the additional Icc per input pin about? And why is it at Vcc - 2.1V?
Sorry if it's a dumbo question. Ta for any hints.
I thought that might be the case (honest ;) but only just before I read your post. Thanks. So I need to calculate the amount of time the inputs spend in this halfway point. Should be easy enough.
On a sunny day (Tue, 14 Jul 2009 13:10:57 +0100) it happened "OldGit" wrote in :
Have not read that datasheet, but likely when halfway 'on' both of some MOSFETS (pull up + pull down) are partly on, so then it draws some power.
I know, my PC clock is wrong. Corrected now (I hope).
some power.
I would think that it's the minimum high level input voltage that you might expect when interfacing to TTL (and the resultant current due to the voltage being 'halfway on', as noted above).
some power.
Jan is right about "half way on". The input inverter (even that of a Schmitt trigger such as the 74HC14) will conduct substantial quiescent current when the input pin resides in the middle. The middle is defined by the IC designers, for HC logic it is truly in the middle, meaning at VCC/2.
is
some power.
The spec for "middle" is actually 30%-70% :-(
In my custom designs I often make such input devices either quite long or use current sources and sinks to limit "overlap" current.
...Jim Thompson
is
some power.
Yeah, you's guys are always +/-8dB while us guys limit ourselves to
+/-3dB :-)
When it comes to very speedy devices the chip designer is probably between a rock and a hard spot.
is
some power.
Wouldn't "speedy" imply very little time spent in the overlap region?
Only slow stuff, or stuff that can float around, requires such limiting.
...Jim Thompson
2.1V,
why is
draws some power.
Sure, but when the input signal isn't always under your control the overlap region remains a concern. I get that question over and over again: "Why is this draining the battery so fast" ... measure, measure, measure ... "Well, those two inputs are not anywhere close to logic levels" ... "But it's a Schmitt" ... "Doesn't matter, the input inverter still seeps" ... "Oh".
2.1V,
why is
draws some power.
You need to learn to speak harshly to your customers when they're doing dumb-ass things ;-)
Of course, in my case, I can contrive my own frontend to prevent/solve such issues.
...Jim Thompson
2.1V,
why is
draws some power.
Nope, old rule: Always be mild-mannered and never point fingers, consultants aren't supposed to run around with smirky faces :-)
Lucky you. I sometimes have to interface with stuff where I get sick when I see it the first time.
: 2.1V,
why is
draws some power.
I didn't know that
Of course. But there _can_be_ off-the-shelf fixes. Ask me the next time you run into such a situation (free home demonstration ;-)
...Jim Thompson
Is the tool du jour to fix it a Beretta or a Glock?
:-)
No! No! Try me. I can likely suggest off-the-shelf components for such situations ;-)
...Jim Thompson
2.1V,
why is
draws some power.
No, you speak softly and carry a big bill.
But, "speedy" and long devices (and other protection means) don't tend to go together. C == bad
: 2.1V,
why is
draws some power.
All my "floaty" inputs are slow.
...Jim Thompson
: 2.1V,
about
And why is
draws some power.
Because you do that simple analog crap, you can afford to be slow [*]. ;-)
[*] Now that I'm retired, I can too.: 2.1V,
about
And why is
draws some power.
defined
at
Speak for yourself. As recently as two years ago I was doing stuff at
5.5GHz ;-)A present project includes a 500MHz VCO.
...Jim Thompson
"OldGit"
:- 2.1V,
about
And why is
it draws some power.
to
quiescent
defined
at
I did. You didn't do that with long channel FETs or current limiting input devices.
Same.
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