Theoretically it should be maximum at the design center of the TTL threshold, ~1.4V.
Maybe the 0.9V you measure is just process skew?
...Jim Thompson
Theoretically it should be maximum at the design center of the TTL threshold, ~1.4V.
Maybe the 0.9V you measure is just process skew?
...Jim Thompson
It's generally quite poorly documented, and varies across vendors, and Logic families. The Schmitt devices tend to have lower peaks than non schmitt devices. Seems to be an after-thought to most digital designers....
-jg
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