3.3v <> 5v interfacing @ 15Mhz

Hi Alison,

Thanks for the reply.

You might find breadboarding a lot more pleasant once you get the hang of working with copperclad. It certainly makes working with high frequency a lot easier, and a well-made board can even be used in place of a pcb. I like to use ordinary hot glue to mount components to the copper. This works great for parts that stay cool:)

I'm still using prototypes I made years ago, and they work fine.

Good luck with your circuit!

Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Keep it up. Everybody is realizing the "value" of your consultancy ;-)

You read a data sheet without understanding.

...Jim Thompson

Hey f*****ad. I re-designed those parts for ON-Semi.

You are clueless as to good engineering practice.

...Jim Thompson

If you have something meaningful to say, then go ahead and tell us. Otherwise have the courage to admit that you just made a fool of yourself, my dear analog desiner.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

Correction: ViH min 2.0V ViL max 0.8V

A lot of noise, no information whatsoever. It is a sign of weakness and I forgive you. Be at peace with yourself.

Apply +2.4V Input to an HCTxx running on VDD = +5V and what happens?

...Jim Thompson

And piece be with you also... GFY ;-)

...Jim Thompson

Jim Thompson a écrit :

Well, you can't expect a digital guy to know that.

Hmmm, gave me an idea :-)

Nothing happens. The 2.4V reads as a clear 1, the threshold is at 1.4V

Jim , you goofed up and I suggest you to bring your apologies.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

Allowing a static (and *undefined* BTW... 1mA if you're lucky) current flow is NOT good engineering practice, and it's NEVER done in well-designed ASIC's.

To see how a 3.3V Logic Level to 5V Logic Level Translator is done properly (in ASIC's designed specifically for that purpose), see...

Dimensions are "pre-shrink" BTW, as if you'd know what that means ;-)

I used a similar scheme in my USB interface work for Intel. Unfortunately the patents don't show that part, since it's old art.

Expect my apologies about the time Russia actually becomes a Democracy and Iran becomes Jewish ;-)

...Jim Thompson

Also: Static current for this structure is zero, except for nA's of leakage.

...Jim Thompson

Jim, your schematic is lacking the power details. How are the HC04 powered ? +3.3V or +5V ?

Rene

From InverterVDD... Those PSpice-provided inverter symbols utilize "hidden" power pins.

In the USB ASIC there weren't actually full 74HC04 equivalents, just single-stage min-geometry inverters... going on into the ASIC... i.e. no heavy loading.

...Jim Thompson

RTFM.

electrical characteristics over recommended operating free-air temperature range

?ICC(*), One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC,

(*) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

Irrelevant. There was a very specific problem, and HCT/AHCT is a correct solution.

Very few people can accept their own mistakes, unfortunately. Life would be much better otherwise.

Yuriy,

You are correct. Here's more supporting documentation.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ AHC/AHCT Designer's Guide

September 1998, revised February 2000

Starting on page 19:

To process signals having a swing of only about 3 V in a system with a supply voltage of 5 V, the TTL-compatible SN74AHCT14 Schmitt trigger is available. This device has the same switching characteristics as the previously described Schmitt trigger, except that appropriate circuitry shifts the switching thresholds into the region of the commonly used TTL-voltage levels. Figure 5 shows the transfer function of such components.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SN54/74HCT CMOS Logic Family Applications and Restrictions

Power Consumption of HCT Circuits

The threshold voltage of a CMOS circuit is determined by the geometry of the input transistors. These transistors are designed to sink the same input current at the required threshold voltage. The resulting voltage at the output is equivalent to 50% of the supply voltage VCC. For an HC circuit, the channel width of the p-channel transistor of the input is approximately twice the value of an n-channel transistor. The purpose is to make both transistors have the same current characteristics, thus making the threshold voltage of their input at about 50% of the supply voltage VCC. This circuit area has been modified for HCT devices: the n-channel transistor is about seven times wider than the p-channel transistor (see Figure 6). This shifts the threshold voltage in a way that it amounts to 30% of the supply voltage. At a supply voltage VCC = 5 V, the threshold voltage is VT = 1.5 V, similar to the threshold voltage of TTL circuits.

Figure 6. Input-Stage Structure of HC and HCT Circuits

Figure 7. Supply Current as a Function of the Input Voltage

Figure 8. Current Consumption as a Function of Frequency

For frequencies above 5 MHz, this effect is of secondary importance, since current consumption is then determined primarily by the power required for reversing the charge of the load capacitance. Moreover, the increase of current consumption for devices driven by TTL levels is much lower in practice because TTL circuits supply a typical voltage swing that is significantly higher than the data sheet value used for the measurement in Figure 8.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Regards,

Mike Monett

Antiviral, Antibacterial Silver Solution:

Alison,

is a explanation of the different logic level voltage translation methods and ICs.

I think that in the non-ASIC world where adding extra transistors is not free, it is less frowned-upon to allow CMOS logic to draw continuous supply current. I don't know of any chips failing due to doing this, with the exception of 74AC series when running from 5V and biased at the threshold, which really does draw a lot of current.

OnSemi do in fact recommend the use of HCT14 devices to receive signals from LSTTL chips (see for yourself.... perhaps their marketing dept needs re-education):

The datasheet "Recommended Operating Conditions" explicitly specifies that there is no minimum input slew rate, and the supply current with one input held at 2.4V is specified as 2.4mA (typ), implying that it is at least an allowable operating condition. Certainly 2.4mA is far below the specified maximum IDD for the part.

It seems to me that the HCT14 will work, and not fail prematurely, when one inverter is driven by a 3.3V input signal. Perhaps you know better, and if so I'd like to hear about it.

I think your circuit with no steady state current consumption would be ideal if one were designing an ASIC, but the intended application is not battery powered, and the HCT parts are cheap, available from several sources, less likely to be discontinued than an exotic level shifter IC, and result in lower component count than using an additional CD4007 (which would probably be too slow anyway when it's required to go to 15MHz). BTW why is the simulated waveform from your CD4007 circuit so fast? Perhaps you don't have PCB parasitics in your simulation. Most manufacturers of 4007 parts seem to specify about 60 - 75ns maximum propagation delay at 5V VDD. I wonder if anyone makes a CD4007 type thing in a more modern process.

Chris

If you're comfortable with that "overlap" current, go right ahead.

I still consider it bad engineering practice but, then again, I'm presently designing a chip (analog, but LOTS of logic) with a total average power consumption specification of 6uA. Overlaps like that would kill the consumption.

I do note that the TI app-note does recommend the Schmitt. But it depends on the Schmitt design whether you still have the overlap current or not.

If 'HCT04 were a good general solution to 3.3V to 5V translators, wonder why they make true translator chips like the Maxim MX3xxxx to name just one? For their health? I doubt it.

...Jim Thompson

Hi Rickman,

It's looking alot tidier now. Should keep me going with the firmware development until the PCBs appear.

The board with the chip on it has most of what's required SPI side condensed down. There's a board under that takes care of getting the Vdd/Vss to the all of the pins (PICs are picky about that). And the ribbon cable goes off to a kind of hybrid SCSI bus implemented on a 68000 processor DMA bus.

Thanks again for your help :-) Thanks to all of you :-)

Alison