24-bit 100kHz A-D converter with optical output

Is this actually for audio? The on-board voltage reference might have a lot of lf noise if you want real precision. Audio doesn't matter: the source s/n is nowhere near 20 bits.

Look out for magnetic pickup loops, too, espacially if there will be fans nearby.

Does jitter matter much to delta-sigmas? They average a lot of events.

John

They solve that with a filter-cap node in the reference pathway.

No, not audio - it's a five-channel capacitance position gauge. But its likely 18 to 19 bits of signal robustness will suffice.

That's a good suggestion. The environment will be magnetically quiet, except for a rather noisy switch-mode linear motor. :>( That's clearly a significant PCB-layout issue. Hmm.

Indeed. The monster-cable crowd says it matters. I wish I knew.

--
 Thanks,
    - Win

I'll second that :>(

On the dac board we just did, the bottom range is +-25 uV full scale. It's VME, and there's typically a fan tray at the bottom of the cardcage. We got similar induction levels for 120 vac and dc brushless fans, in the ballpark of 1 uV per square cm of loop area for the channels closest to the fans, so loop area minimization was a prime consideration in parts placement and routing.

You might consider filtering the power drive to the motor some. Both the mag field and the spikes could be nasty around low-level stuff.

John

Hi Win, We used the (pre-release) CS5372 24bit ADC with a CS3302 front end diff amp, a CS4373 24bit test DAC, ADG734 MUXes, and an AD780 reference. This was for a 10,000+ channel seismic data aquisition system.

CS5372

CS3302 CS4373

Much to the surprise of the Cirrus guys we got better performance than the their "reference" board in a direct A-B comparison. From memory I think we got typically

Jitter.....

hi Win, just been looking at the DICE,cos i ran out of beer

they seem to improve jitter perfomance, but it's a bit over above comprehension at the mo, sorry

martin

On 18 Sep 2005 15:26:36 -0700, Winfield Hill wroth:

There are very few designers who can do justice to a 24-bit converter.

That's the bad news.

Now for the good news..........

There are even fewer people who can properly test a 24-bit design.

Take your best shot. Nobody will ever be able to prove it doesn't do what you say it will.

Jim "I am *not* kidding." Meyer

Whew, did you have 10,000 A-D converters?

Thanks for the great story, that's encouraging!

Roger willco.

--
 Thanks,
    - Win

Divide (by 100) down to 100kHz, multiply up (by 128) to 12.8MHz? Or divide down (by 25) to 400kHz, multiply up (by 32) to 12.8MHz?

If jitter matters to you and you have to be PLL locked to that 10MHz, I would advise that you use a simple varactor-tuned LC VCO.

Otherwise just get a 12.8MHz crystal (off-the-shelf frequency) and avoid all that PLL crap.

How did your DDS PCB layout go? You didn't actually believe AD's spec for the size of the AD9953 die ground pad did you? :-).

Tim.

That's it. Higher reference frequencies are better, right?

Good advice, I don't know if it matters that much.

No choice, I have to lock to an external precision time reference.

I made it 0.20" square, with a 0.11" hole in the middle to reach in with a soldering iron... Crude, but... What do you suggest?

--
 Thanks,
    - Win

I read in sci.electronics.design that David L. Jones wrote (in ) about '24-bit 100kHz A-D converter with optical output', on Sun, 18 Sep 2005:

How was it for EMC emissions? The Cirrus stuff often has extremely fast edges, which delight in escaping from whatever enclosure you put them in.

--
Regards, John Woodgate, OOO - Own Opinions Only.
If everything has been designed, a god designed evolution by natural selection.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

Yeah, a big Seismic boat (for deep water oil exploration) can tow 8 or more "streamers" up to 8-10km in length each. Each streamer can have a thousand or more Hydrophone channels spaced at regular intervals. Each channel has to have a 24bit ADC, 24bit test DAC, and associated switching to allow for full testing of THD, noise, sensor capacitance, leakage and so on. Cost just for the front end electronics alone is in the order of US$100/channel. All the channels across all the streamers must be fully syncronised and sampled continously in real-time. The boats operate 24/7 for months on end.

Interestingly, the system size is ultimately limited by the power consumption. Losses over 10km of streamer are huge, 500VDC in one end,

We didn't have to worry about any of that :-P These are used in the ocean so no need to meet any commercial EMC requirements apart from it not interfering with itself. Sharks do like to bit them though, but we aren't sure if that's becuase of the emmissions or that they are simply a yellow colour :->

Dave :)

I'm interested in the 100-500V input DC-DC converter, what output voltage(s) did it have, how'd you keep it quiet enough to work with the 24-bit A/Ds? Was its clock synchronized with the A/D clock?

--
 Thanks,
    - Win

We used a two tier power system

1) A 100-500VDC to 12VDC converter for some global electronics, and a 100-500VDC to 100VDC converter for phantom power on the data lines which connected and powered the aquisition modules. 2) A 100VDC to 3.3VDC converter for the local aquisition digital stuff, and then a +3V LDO (MIC5255) for positive analog plus a switched cap inverter (LM2662) and -3V LDO (MAX1735) for the negative analog.

All of the flyback converters and the switched cap inverter were synchronised with the telemetry clock from which the sampling clock was derived. So the entire system was syncronous.

Add some physical seperation, bare bones filtering, and the balanced inputs on the diff amps and ADC, it wasn't a problem. No shielding was required.

Dave :)

If jitter really does matter to you, then a PLL with a VCO made from a crystal oscillator with a varactor for fine tuning (VCXO) would be the quietest choice I think. To me the appeal of the VCXO PLL approach is that there can be quite a lot of noise or ripple on the tuning input of the VCXO and it still doesn't affect the output much because KVCO is so low. The tuning range only needs to be as large as the drift of the crystal plus the drift of the 10MHz reference. I would probably try to run the crystal at a multiple of 12.8MHz and follow that with a CMOS divider.

Chris Jones